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Patent Searching and Data


Title:
SQUELCH CIRCUIT
Document Type and Number:
Japanese Patent JPS61248625
Kind Code:
A
Abstract:

PURPOSE: To improve the quality of a reception signal by applying squelch operation to a demodulation circuit reaching a prescribed value of reception level or below after a prescribed delay time, sampling-and holding the demodulation signal within a delay time up to the squelch operation and applying a voltage subjected to sampling and holding after the squelch operation thereby eliminating impulsive noises generated at the output terminal.

CONSTITUTION: When an FM demodulation signal is inputted and an analog switch 10 is in open control after a time corresponding to a time constant τ2 elapses and then squelch operation is started, a feeding line to a buffer amplifier 8 is changed over to the position of a sample-and-hold circuit 18 connected via an analog switch 17 and the buffer 8 and a voltage is fed to the buffer amplifier 8 according to the discharge of the voltage of the capacitor of a sample-and-hold circuit 18. Through the switching control above, the power is fed to the buffer amplifier 8 for the discharge time constant of the sample- and-hold circuit 18. Thus, the output of the buffer amplifier 8 is attenuated gradually attended with the power application and a cause of the impulsive noise generation is eliminated.


Inventors:
HATAKEYAMA AKIHIRO
Application Number:
JP8881885A
Publication Date:
November 05, 1986
Filing Date:
April 26, 1985
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H04B1/10; (IPC1-7): H04B1/10
Attorney, Agent or Firm:
Noriyuki Noriyuki