PURPOSE: To reduce the error voltage by using an auxiliary capacity provided in parallel with a capacitor of the main body and the main capacitor so as to branch an error voltage due to clock feed-through having voltage dependancy.

CONSTITUTION: Since an auxiliary capacitor D is provided in parallel with a capacitor A storing an input signal charge, the clock feed-through caused by a switch B is branched into two capacitors A, D. On the other hand, the input signal charge stored in the capacitor A depends on the input voltage fed to the capacitor A itself and independently of the presence of the auxiliary capacitor D. Thus, the ratio with respect to the signal charge of the clock feed-through flowing to the capacitor A is reduced remarkably. Thus, the effect of the error voltage superimposed on the output signal onto the input voltage is reduced and the highly accurate circuit design is realized by eliminating the fluctuation of the frequency characteristic.