To provide a timing analyzing device, etc., which quantitatively finds clock timing having possibility of generating a violation clock.

An integrated circuit equipped with 1st and 2nd synchronous circuits which operate with 1st and 2nd clocks and an asynchronous circuit is a timing analysis system which analyzes the clock timing of an integrated circuit in which the output of the 1st synchronous circuit is inputted to the asynchronous circuit, and the output of the asynchronous circuit is inputted to the 2nd synchronous circuit. This analysis system stores circuit description information prescribing the connection relation among circuit elements, delay information prescribing the delay time when data are propagated, and clock restriction information prescribing conditions of 1st and 2nd clocks, analyzes the data delay time of the asynchronous circuit from the circuit description information and the delay information, and specifies the clock timing of the 2nd clock where an operation timing error of the 2nd synchronous circuit is caused from the data delay time and the clock restriction information.