Title:
TEST METHOD AND DEVICE FOR WIRING ON SEMICONDUCTOR INTEGRATED CIRCUIT CHIP
Document Type and Number:
Japanese Patent JP3239839
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To enable detecting anomaly of wiring in lower layer of multiple layer wiring by supplying an integrated circuit with electric power, irradiating the scanning region on the integrated circuit including the wiring, detecting current change at each scanning point and observing the current passing state in the wiring.
SOLUTION: After moving a sample stage 7 and moving a sample 6 to the irradiation position of laser beam, power is supplied from an electric source 8 to the sample 6, laser beam 5 generated in a laser beam generator 4 is irradiated and scanned to the observation region of the sample 6. A current change detector 9 detects the current change at each scanning point of longitude 512 ×width 512, for example, in the sample 6. An image indicator 10 converts the voltage value in each point in the sample 6 to brightness information or pseudo color information and indicates it with 256 steps colors on each point on CRT screen corresponding to each scanning point. By this, current flowing in the wiring of the integrated circuit can be observed, and from the change, an anomaly especially in the wiring in lower layer can be detected.
More Like This:
Inventors:
Kiyoshi Futagawa
Application Number:
JP11801998A
Publication Date:
December 17, 2001
Filing Date:
April 28, 1998
Export Citation:
Assignee:
NEC
International Classes:
G01R31/302; H01L21/66; G01R31/02; (IPC1-7): G01R31/302; G01R31/02; H01L21/66
Domestic Patent References:
| JP8160095A | ||||
| JP6300824A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)