TIMING PULSE GENERATING CIRCUIT

Title:

TIMING PULSE GENERATING CIRCUIT

Document Type and Number:

Japanese Patent JP2943750

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To reduce a memory capacity by obtaining a timing pulse repeated in a horizontal direction and a timing pulse repeated in a vertical direction from separate ROMs.
SOLUTION: Pulses SH1, SH2 repeated in a horizontal direction are outputted from a horizontal ROM circuit 65 and a pulse SH3 specifying a vertical transfer period, that is, a period not outputting horizontal transfer clocks H1, H2 is outputted. Furthermore, a pulse Sv1 repeating in a vertical direction at a low level corresponding to a read period of a CCD solid-state image pickup element 3 for odd and even numbered fields is outputted from a vertical ROM circuit 69. Thus, the horizontal repetitive pulses SH1-SH3 are obtained from the horizontal ROM circuit 65 and the vertical repetitive pulse Sv1 is obtained from the vertical ROM circuit 69 in this way, then the data quantity written in each ROM of the horizontal ROM circuit 65 and the vertical ROM circuit 69 is reduced.

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Inventors:

YAMAGUCHI MASANORI
SATO MAKI

Application Number:

JP391097A

Publication Date:

August 30, 1999

Filing Date:

January 13, 1997

Export Citation:

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Assignee:

SONII KK

International Classes:

H04N5/335; H04N5/341; H04N5/372; H04N5/376; (IPC1-7): H04N5/335

Domestic Patent References:

JP59190782A

Attorney, Agent or Firm:

Hidekuma Matsukuma

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