Title:
METHOD FOR POSITIONING SEMICONDUCTOR WAFER
Document Type and Number:
Japanese Patent JPS607120
Kind Code:
A
Abstract:
PURPOSE:To easily perform the positioning of the titled wafer by a method wherein V-shaped cutouts are formed at the ends of peripheral edges on reference lines intersecting at the center of the wafer or the reference point set separately. CONSTITUTION:In the peripheral edges of the wafer 2, the V-shaped cutouts 6A, 6B, 6C and 6D are formed on the reference lines 4A and 4B passing through the center O of the wafer 2 and intersecting rectangularly. Using a mask 10 at the time of exposure of photo resist, exposure is carried out by fitting the ends of cross lines 8A and 8B to the tops of the cutouts 6A, 6B, 6C and 6D. Next, the wafer 2 is developed and etched, and resist is applied again over the surface. Thereafter, exposure is carried out by fitting cross lines 14A and 14B to the cutouts 6A, 6B, 6C and 6D with the wafer upside down or by means of a mask 12 from the lower surface.
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Inventors:
AKIYAMA MASAYOSHI
Application Number:
JP11465283A
Publication Date:
January 14, 1985
Filing Date:
June 25, 1983
Export Citation:
Assignee:
ROHM KK
International Classes:
H01L21/02; H01L21/68; (IPC1-7): H01L21/02
Domestic Patent References:
| JPS5651839A | 1981-05-09 | |||
| JPS5383574A | 1978-07-24 |
Attorney, Agent or Firm:
Shoichi Unemoto
Next Patent: JPS607121