Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS5840839
Kind Code:
A
Abstract:
PURPOSE:To generate no Si3N4, etc. on an element forming region, by performing a heat treatment after covering the element forming region on a substrate with a laminated film of an SiO2, a polycrystalline Si and an Si3N4, and forming channel stopper regions in the substrate on the both thereof by an ion implantation, when forming a thick field oxide film in the periphery of the semiconductor substrate. CONSTITUTION:An SiO2 film 12, a polycrystalline Si layer 13 and an Si3N4 film 14 are generated in lamination on a P type Si substrate 11, and a resist pattern 15 is provided on the element forming region. Next, an etching is performed down to the Si layer 13 with the pattern as a mask, and thus a laminated pattern 16 constituted of the layer 13 and the film 14 is survived only on the element forming region. Thereafter, P type impurity ions are implanted on the both end of the pattern 16 through a film 12 which is exposed, and thus an inversion preventing treatment of a field region is performed on the surface layer of the substrate 11. Next, the pattern 15 is removed, a weight oxidation is performed on the substrate 11 resulting in the generation of a field SiO2 film 17 underlaying P<+> type inversion preventing regions 18 on both side of the pattern 16.
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Inventors:
TAKESHITA YUUJI
Application Number:
JP13934781A
Publication Date:
March 09, 1983
Filing Date:
September 04, 1981
Export Citation:
Assignee:
TOKYO SHIBAURA ELECTRIC CO
International Classes:
H01L21/76; H01L21/316; H01L21/762; (IPC1-7): H01L21/94
Domestic Patent References:
| JPS54137982A | 1979-10-26 | |||
| JPS5670644A | 1981-06-12 | |||
| JPS56104468A | 1981-08-20 |
Attorney, Agent or Firm:
Takehiko Suzue