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Patent Searching and Data


Title:
DMA CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS60160460
Kind Code:
A
Abstract:

PURPOSE: To attain the DMA control even in case plural input/output devices are connected to a channel by setting the flag information to a desired input/output device column belonging to a desired channel provided to a control table and then updating said flag information.

CONSTITUTION: A processing part 5 of a processor 1 sets the information 1 to a column F1 of a control table 4 and then sends an enable signal E to an input/ output device I1. A DMA control part D1 performs the writing/reading of data to a memory 6 through the device I1. When this access is over, the part D1 sends an end signal G to the processor 1. The part 5 refers to a time control part 2 to discriminate that the signal G is delivered from the device I1. Then the part 5 updates the information of the column F1 and then transmits again the signal E to an input device I2.


Inventors:
MATSUMORI KUNIHIKO
YANAGISAWA TSUTOMU
Application Number:
JP1564784A
Publication Date:
August 22, 1985
Filing Date:
January 31, 1984
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F13/28; (IPC1-7): G06F13/28
Attorney, Agent or Firm:
Sadaichi Igita



 
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