PURPOSE: To obtain a high withstand voltage MIS device of fine pattern by a method wherein a P- layer 2 is provided in an N type Si substrate, then a P- layer is formed over a part of the exposed part of a P-N junction, and a thick isolation oxide film is provided simultaneously with forcing diffusion.

CONSTITUTION: The P- layer 2 is provided in the N type Si substrate 1, then Si3N4 films 14a and 14b are formed on an SiO2 film, and the inside and outside of the P- layer 2 are covered. Next, a photo resist mask 11 is applied, thus P type impurity ions 3 are selectively implanted in self-alignment into the boundary region 10' between the P- layer 2 and the N type substrate 1, and the substrate 1 is oxidized resulting in the formation of the thick isolation insulation film 5. Meantime, the impurity of the region 10' diffuses, and thus the P- layer 10 is formed. After removing the Si3N4 films 14a and 14b, a gate oxide film 6 and a poly Si gate electrode 7 are formed, and a P+ type drain 8 and source 9 are formed in self-alignment with the electrode 7 and the insulation film 5 as masks. By this constitution, the electric field in a drain side P-N junction is small, and that between the drain and the gate is small. Therefore, desired characteristics can be obtained, since drain withstand voltage and the insulating strength of the gate are high, and there is less change of channel lengths.