Title:
WIRING BOARD AND ITS MANUFACTURE
Document Type and Number:
Japanese Patent JP3470789
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To improve reliability of electrical connection between pads, by reducing occurrence of voids in solder at the time of connecting a flip chip by appropriately setting the plating thickness of a ceramic wiring board.
SOLUTION: Metallized layers 4 which become pads 11 when the layers 4 are connected to via holes 3 are formed on one main surface of an alumina ceramic board 2 by simultaneously baking the layers 4 with the board 2. Then the pads 11 are formed by coating the layers 4 with plated-nickel layers 5 having thicknesses of 2.5-8 μm and the layers 5 with plated-gold layers 6. Consequently, the base metallized layers 4 of the pads 11 formed on a wiring board 1 are nearly completely coated with the plated-nickel layers 5. Therefore, the reliability of electrical connection between the pads 11 can be improved, because occurrence of voids in a solder connecting the pads 11 to each other can be reduced after a flip chip of an integrated circuit chip is connected without causing peeling of the metallized layers 4 nor cracks between the layers 4 and the board 2.
More Like This:
Inventors:
Hiroyuki Hashimoto
Kazuhisa Satoh
Kazuhisa Satoh
Application Number:
JP29937397A
Publication Date:
November 25, 2003
Filing Date:
October 15, 1997
Export Citation:
Assignee:
Nippon Special Ceramics Co., Ltd.
International Classes:
H01L21/60; H05K1/09; H05K1/11; H05K3/24; (IPC1-7): H01L21/60
Domestic Patent References:
| JP8306816A | ||||
| JP6343335A |
Attorney, Agent or Firm:
Kazuhisa Kato
Previous Patent: INSTALLING METHOD AND INSTALLING DEVICE OF RESIN-MADE ATTACHMENT
Next Patent: PHOTODETECTOR ARRAY
Next Patent: PHOTODETECTOR ARRAY