Title:
WIRING BOARD
Document Type and Number:
Japanese Patent JP3323060
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To prevent the generation of chips, breaks and cracks in insulation boards even when wiring boards comprising them collide violently with each other or the wiring board collides violently with some portion of a semiconductor device manufacturing line, by forming each insulation board through binding inorganic insulation powder with a thermosetting resin having an excellent toughness.
SOLUTION: In this wiring board, a plurality of insulation layers 1a-1e made of 60-95wt.% inorganic powder bound with a 5-40wt.% thermosetting resin are laminated up and down, and a wiring conductor 2 made of metallic powder bound with a thermosetting resin is interposed between the insulation layers 1a, 1b. In this case, the dielectric constants of at least one layer of the insulation layers 1a-1e are made not smaller than 20, and on the respective top and bottom surfaces of at least one layer of the insulation layers with respective dielectric constants not smaller than 20, respective pairs of opposite electrodes 5 to each other each pair of which sandwiches the insulation layer with a dielectric constant not smaller than 20 between them are disposed respectively.
More Like This:
Inventors:
Hidenori Shikata
Application Number:
JP13193496A
Publication Date:
September 09, 2002
Filing Date:
May 27, 1996
Export Citation:
Assignee:
Kyocera Corporation
International Classes:
H05K1/03; H01L23/14; H05K3/46; (IPC1-7): H01L23/14
Domestic Patent References:
| JP677649A | ||||
| JP7122681A | ||||
| JP851283A |