Title:
A manufacturing method of a semiconductor device and a semiconductor device
Document Type and Number:
Japanese Patent JP6081790
Kind Code:
B2
Abstract:
A structure including an oxide semiconductor layer which is provided over an insulating surface and includes a channel formation region and a pair of low-resistance regions between which the channel formation region is positioned, a gate insulating film covering a top surface and a side surface of the oxide semiconductor layer, a gate electrode covering a top surface and a side surface of the channel formation region with the gate insulating film positioned therebetween, and electrodes electrically connected to the low-resistance regions is employed. The electrodes are electrically connected to at least side surfaces of the low-resistance regions, so that contact resistance with the source electrode and the drain electrode is reduced.
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Inventors:
Atsushi Isobe
Hiromitsu Goto
Hiromitsu Goto
Application Number:
JP2012275834A
Publication Date:
February 15, 2017
Filing Date:
December 18, 2012
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L29/786; H01L21/28; H01L21/336; H01L21/8242; H01L21/8244; H01L27/105; H01L27/108; H01L27/11; H01L27/115; H01L29/417; H01L29/423; H01L29/49; H01L29/788; H01L29/792
Domestic Patent References:
| JP2007073663A | ||||
| JP2009520367A | ||||
| JP2008028263A | ||||
| JP5075127A |
Foreign References:
| US20100140608 | ||||
| US20090096002 |