Title:
【発明の名称】浮遊電流の少ない高電圧半導体素子
Document Type and Number:
Japanese Patent JP3163674
Kind Code:
B2
Abstract:
The present invention relates to a high voltage semiconductor device comprising a weakly doped (N<->) central region flanked by layers (P1, P3) of higher doping level forming with the central region first and second junctions (J1, J2) capable of supporting the said high voltage, in which device the first and second junctions are flush with a same main surface of the device, on either side of a visible surface of the said central region, and in which device a furrow is formed in the whole of the said visible surface and is filled with a passivation glass (18). The surface of the glass is covered, above the contour of each junction, with a metallisation (21, 22) in contact with the layer corresponding to this junction.
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Inventors:
Francis Pauline
Application Number:
JP23241391A
Publication Date:
May 08, 2001
Filing Date:
August 21, 1991
Export Citation:
Assignee:
STMicroelectronics Society Anonymous
International Classes:
H01L29/06; H01L29/40; H01L29/74; H01L29/747; (IPC1-7): H01L29/74
Domestic Patent References:
| JP358429A | ||||
| JP2125468A | ||||
| JP1274471A |
Attorney, Agent or Firm:
Keiichi Yamamoto