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Title:
3D IMAGE SIGNAL PROCESSING DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/030914
Kind Code:
A1
Abstract:
For 3D display, if the frequency obtained by multiplying the input clock by 2 exceeds the maximum transmission speed to a cinema display circuit (104), the clock multiplication factor is lowered from multiplication by 2 and the output horizontal total clock number is reduced accordingly.

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Inventors:
HAMAMURA SHIGEO (JP)
Application Number:
PCT/JP2011/069425
Publication Date:
March 07, 2013
Filing Date:
August 29, 2011
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Assignee:
NEC DISPLAY SOLUTIONS LTD (JP)
HAMAMURA SHIGEO (JP)
International Classes:
H04N13/04
Domestic Patent References:
WO2011039852A12011-04-07
Foreign References:
JP2010034704A2010-02-12
JP2010028261A2010-02-04
JP2008197141A2008-08-28
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (JP)
Akio Miyazaki (JP)
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