Title:
ARCHITECTURE WITH MULTI-INSTANCE REDUNDANCY IMPLEMENTATION
Document Type and Number:
WIPO Patent Application WO2001041150
Kind Code:
A3
Abstract:
A semiconductor memory architecture for embedded memory instances (204A, 204B) having redundancy. A fuse box register (206) is provided outside the memory macro associated with the memory instances. The memory instances are daisy-chained to the fuse box register (206) containing a plurality of fuses (302) used for storing fuse data associated with the defective rows and columns of the memory. During power-up or after blowing the fuses, the contents of the fuses (i.e., fuse data) are transferred to a plurality of volatile redundancy scan flip-flops (304). The fuse box (206) is then deactivated to eliminate quiescent through the fuses (302). The redundancy scan flip-flops (304), connected in a scan chain, are located inside the fuse box (206) as well as the memory instances (204A, 204B). During the shifting mode of operation, the fuse contents are scanned into individual flip-flops, organized as scan registers (208A, 208B) for row redundancy and column redundancy, of the memory instances. Redundant elements are pre-tested by bypassing the fuses (302) and directly scanning in arbitrary patterns into the redundancy scan flip-flops (304) (override mode operation).
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Inventors:
SHUBAT ALEX
HONG CHANG HEE
HONG CHANG HEE
Application Number:
PCT/US2000/042421
Publication Date:
December 13, 2001
Filing Date:
November 30, 2000
Export Citation:
Assignee:
VIRAGE LOGIC CORP (US)
International Classes:
G11C29/00; (IPC1-7): G06F11/20; G11C29/00
Foreign References:
| EP0867810A2 | 1998-09-30 | |||
| US5255227A | 1993-10-19 | |||
| US5301153A | 1994-04-05 | |||
| US5668818A | 1997-09-16 | |||
| EP0158006A2 | 1985-10-16 |
Other References:
See also references of EP 1236207A2
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