ARRAY SUBSTRATE, PREPARATION METHOD THEREFOR, AND DISPLAY PANEL

Title:

ARRAY SUBSTRATE, PREPARATION METHOD THEREFOR, AND DISPLAY PANEL

Document Type and Number:

WIPO Patent Application WO/2017/133097

Kind Code:

A1

Abstract:

An array substrate, a preparation method therefor, and a display panel. The array substrate comprises a base substrate (100) and comprises a first conductive layer (101), an insulation layer (102) and a second conductive layer (103) that are sequentially located on the base substrate (100). The insulation layer (102) comprises a via hole region (I), a semi-preservation region (M) located on the outer side of the via hole region (I), and a total-preservation region (O) surrounding the region where the semi-preservation region (M) and the via hole region (I) are located. Because the surrounding region of the via hole region (I) is the semi-preservation region (M), the thickness of the insulation layer (102) surrounding a via hole is lowered, and the impact of residual insulation layer materials on the edge of the via hole can be lowered; besides, the height range difference of the insulation layer (102) is divided into two segments, so that the range difference impact caused by the overall thickness of the insulation layer (102) can be lowered.

Inventors:

CHEN CHENG (CN)
LI JILONG (CN)
XU DEZHI (CN)
LV YANMING (CN)

Application Number:

PCT/CN2016/081146

Publication Date:

August 10, 2017

Filing Date:

May 05, 2016

Export Citation:

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Assignee:

BOE TECHNOLOGY GROUP CO LTD (CN)
HEFEI BOE OPTOELECTRONICS TECH (CN)

International Classes:

G02F1/1362; H01L21/768; H01L21/77; H01L27/02

Foreign References:

CN103424915A	2013-12-04
CN103456740A	2013-12-18
CN203502708U	2014-03-26
CN102023429A	2011-04-20
CN105514125A	2016-04-20
CN104280805A	2015-01-14
US20040263742A1	2004-12-30