Title:
CLOCK DISTRIBUTOR CIRCUIT FOR MAINTAINING A PHASE RELATIONSHIP BETWEEN REMOTE OPERATING NODES AND A REFERENCE CLOCK ON A CHIP
Document Type and Number:
WIPO Patent Application WO2004015743
Kind Code:
A3
Abstract:
A clock signal distributor circuit (12) for maintaining a phase relationship between one or more remote operating nodes (15, 17) and a reference clock on a chip, wherein there is a clock signal drive path and a clock signal sense path in a distribution limb (14, 16) for each remote node (15, 17). The clock signal distributor circuit (12) comprises a variable signal delay circuit in the clock signal drive path, a variable signal delay circuit in the clock signal sense path, and a feedback circuit that causes at least one variable signal delay circuit to change its signal delay based on phase of signal on the clock signal sense path.
Inventors:
CARLEY ADAM L
Application Number:
PCT/US2003/024315
Publication Date:
June 17, 2004
Filing Date:
August 05, 2003
Export Citation:
Assignee:
TIMELAB CORP (US)
International Classes:
G06F1/10; H03K5/13; H03K5/15; (IPC1-7): G06F17/50
Foreign References:
| US5087829A | 1992-02-11 | |||
| US5043596A | 1991-08-27 |
Download PDF:
Previous Patent: HIGH RATE DEPOSITION IN A BATCH REACTOR
Next Patent: VIA PROGRAMMABLE GATE ARRAY INTERCONNECT ARCHITECTURE
Next Patent: VIA PROGRAMMABLE GATE ARRAY INTERCONNECT ARCHITECTURE