Title:
CLOCK SKEW-ADJUSTABLE CHIP CLOCK ARCHITECTURE OF PROGRAMMABLE LOGIC CHIP
Document Type and Number:
WIPO Patent Application WO/2023/098064
Kind Code:
A1
Abstract:
The present invention relates to the field of clock design. Disclosed is a clock skew-adjustable chip clock architecture of a programmable logic chip. A delay adjustment cell is arranged in a path of at least one regional clock of the chip clock architecture, and the delay adjustment cell comprises a plurality of parallel delay routes having different delay values; the delay adjustment cell gates one of the delay routes according to a configuration signal obtained so that the connected regional clock has a corresponding target delay; the target delay of each regional clock corresponds to a clock skew working mode of a programmable logic chip; the clock skew between different regional clocks can be adjusted by controlling the gated delay route in the delay adjustment cell, so that the clock skew of the chip can be adjusted within a relatively large range; under a same resource configuration, different path selections in the delay adjustment cell will cause different clock skews, so as to satisfy the requirement of different clock skew working modes in different application scenarios.
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Inventors:
KUANG CHENGUANG (CN)
ZHANG YANFEI (CN)
CHEN BOYIN (CN)
FAN JICONG (CN)
ZHANG YANFEI (CN)
CHEN BOYIN (CN)
FAN JICONG (CN)
Application Number:
PCT/CN2022/102672
Publication Date:
June 08, 2023
Filing Date:
June 30, 2022
Export Citation:
Assignee:
WUXI ESIONTECH CO LTD (CN)
International Classes:
G06F1/10
Foreign References:
| CN114167943A | 2022-03-11 | |||
| CN105786087A | 2016-07-20 | |||
| JPH08274602A | 1996-10-18 | |||
| CN107453736A | 2017-12-08 | |||
| US20100117705A1 | 2010-05-13 | |||
| US20080141061A1 | 2008-06-12 |
Attorney, Agent or Firm:
WUXI HUAYUAN PATENT AND TRADEMARK AGENCY (GENERAL PARTNERSHIP) (CN)
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