The invention relates to an integrated circuit comprising a succession of logic network stages, each having an output node and a second node, each stage adapted to be supplied with input logic signals for processing and including driver transistors of one conductivity type, first and second power buses to be maintained at a steady potential difference, a separate precharge transistor of a conductivity type opposite the one type connected between the first power bus and the output node of each stage, the precharge transistor gate being connected to a bus to be supplied with clock signals, and a separate power switch transistor of the one type connected between the second power bus and the second node of each stage, the power switch transistor having its gate connected to a bus to be supplied with the clock signals.

There has been increasing interest in integrated circuits using both n-channel and p-channel enhancement mode field-effect transistors because of the improved noise and low power dissipation properties of such circuits. Hereinafter it should be assumed that all of the transistors included are of the enhancement type unless otherwise indicated. The terms "n-channel", "NMOS", and "n-type" transistor refer to a transistor with an n conductivity type source and drain, while the letter "p" refers to p-type conductivity.

In a fully complementary CMOS circuit in which each p-type transistor is paired with a corresponding n- type transistor, the logic function of each gate is implemented twice, once in the array of p-type transistors and again in the array of n-type transistors. The advantage of using the two complete arrays is that except for the brief time when the outputs or inputs are making transitions no current flows and no power is consumed.

However, the problem of this approach is the large amount

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of area needed to house the two complete arrays of transistors. Moreover, the extra area and the extra transistors result in a large capacitive load which slows the speed of the circuit. For this reason, NMOS technology early became the dominant technology for high speed logic, particularly since an NMOS transistor has a better figure of merit than a PMOS transistor because of the higher mobility of electrons. However, power dissipation can become a problem in large arrays based on NMOS technology.

To maintain the main benefits of CMOS technology without the area penalty of complete duplication of the two arrays, there has been developed the circuit technique known as pseudo-NMOS. Pseudo-NMOS technology is a design technique which uses circuits identical to those in NMOS technology except for the regular substitution of a p- channel transistor for the load or pull-up n-channel transistor. However, a problem with this approach is that pull-up current always flows in the pseudo-NMOS circuit even if the logic network is pulling down. This slows the pull-down. Making the pull-up current very small would not solve the problem because then the pull-up would be very slow. As a result, the speed of CMOS technology and that of pseudo-NMOS technology tends to be nearly the same and the trade-off in choosing one or the other technology is between the low power consumption of CMOS technology and the low area of the pseudo-NMOS technology. As conventionally used, terms such as "pull-up", "pull-down", and "level" refer to relative voltages; e.g., it is common to refer to a voltage increase as a "pull-up to a higher level". The terms "dynamic" as used herein refers to a circuit in which the main current path through the driver transistors is intermittently interrupted by a clock- operated switch, while "static" refers to a circuit that does not require such interruption. "Evaluation" refers to the logic computation phase.

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To achieve circuits which combine both low capacitance and high current capability, various forms of dynamic pseudo-NMOS circuits have been developed. Typically, such a circuit includes a network or cluster of n-type driver transistors interconnected to implement a logic function, a p-type pull-up transistor, and an n-type pull-down or power switch transistor. The pull-up transistor connected between the low level of the power source, typically ground, and the other or second node of the network. In operation, the gate electrodes of the pull-up and the pull-down transistors are clocked together for precharging the output node of the network to a high level while the current path to the low level is turned off because the ground switch is open. Changing of logic inputs to the network occurs during the precharge phase. At the completion of precharge, the clock turns off the pull-r-up transistor and turns on the pull-down transistor to close the ground switch and begin the evaluation phase. Depending on the states of the logic inputs to the network, the output node will either continue to float high or be pulled down to a lower level.

Theoretically the advantage of a dynamic circuit is that its load capacitance is comparable to that of a static pseudo-NMOS circuit but the full pull-down current is available with the result that fast speeds can be realized .

However, there are problems in realizing these supposed speed advantages in practical circuits because such circuits generally have several logic networks in tandem. In the dynamic approach no network can be activated until its inputs have stabilized, and the time allowed for the network to stabilize must be chosen so that even the network with the longest delay can stabilize. Moreover, stabilization is complicated because in each but the first stage the driver coupled to the output node of the preceding stage begins with its input at the high precharge level of the output node of the preceding stage.

Accordingly, it is often necessary to include some provision for delay in the evaluation phase of different drivers of the circuit, and this results in considerable increase in circuit complexity, particularly when many stages are involved.

One approach that has been developed to meet this problem has been described as the CMOS domino circuit. In its preferred form, this technology too, as in the dynamic CMOS, utilizes clusters of NMOS transistors for the logic networks and uses PMOS transistors as precharge or load elements. As in a dynamic circuit, each output node is precharged to a higher voltage while the path to the low level, typically ground, is open and the precharge is stopped when the path to ground is closed. A significant difference is that the transition from precharge to evaluation is accomplished by means of a single clock edge applied simultaneously to all the drivers in the circuit. To make this practical, it is important to assure that in each stage but the first the inputs to any drivers coupled to the preceding stage are all low before the start of the evaluation phase. To this end, a static inverter is included as a buffer between the output node of one domino stage and the input circuit node of the drivers in any next domino stage to be supplied by such output. During the precharge, when the output node is at the high precharge level, the buffer output is low so that all circuit nodes which connect the output of one domino stage to the input of any next domino stage are low and therefore the transistors they drive are off. In addition during evaluation, such an input node of a succeeding domino stage can experience only a single type of transition, namely from low to high. All such input nodes can make at most only such a transition during evaluation and then must stay there until the next precharge when they again can experience only a single type of transition, in this case from high to low. Of course such nodes need not make any transition if they are already at the appropriate level.

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As a result there cannot be any deviations at any nodes in the circuit. Moreover, all the drivers may be switched from precharge to evaluate with the same clock edge.

A pure domino CMOS circuit ideally has the low power of a dynamic circuit since there is never a d-c path to ground. Also the full pull-down current is available to drive the output nodes. At the same time the load capacitance is much smaller than for the standard static CMOS because most of the p-type transistors have been eliminated from the load. Meanwhile, the use of a single clock edge to activate the circuit provides simple operation and full utilization of the speed of each gate.

One limitation is that each but the last stage must be buffered with an inverter but this is not a significant problem since such buffering would generally have been needed for maximum speed.

However, in practice Applicant has found that, in a pure domino circuit, charge tends to leave the output node as a result of leakage or noise and the operation tends to become less reliable, particularly when many stages are involved.

In accordance with the invention, this problem is solved in an integrated circuit as described above charac¬ terized in that an auxiliary precharge transistor of a con- ductivity type opposite the one type is connected between the first power bus and the output node of each logic network stage, the auxiliary precharge transistor having a gate connected to a terminal which is not supplied with clock signals. The sole Figure in the drawing shows an illustrative quasi-static domino CMOS in accordance with an illustrative embodiment of the invention.

Applicant has found it desirable to modify the CMOS domino circuit by the connection between the output node and the high power terminal of an improved form of precharge network. In particular in its preferred form based on NMOS logic networks, Applicant's improved

precharge network includes both the standard p-type pull-up transistor whose gate is clocked to be off during the evaluation phase and an auxiliary trickle-charge p-type transistor in shunt with the standard transistor but whose gate is connected to trickle flow of some current to the output node during the evaluation phase.

In this arrangement, the clocked p-type transistor is chosen to have a large beta for quickly precharging the output node when the circuit is not being evaluated, and the unclocked p-type transistor is chosen to have a small beta to have a small effect on the total pull-down current needed and so the power consumed during evaluation. Preferably this smaller trickle transistor is maintained on continuously by connecting its gate to the low level of the power supply, typically ground.

Alternatively, the gate of the smaller transistor can be tied to the output of the following inverter whereby it is turned off when the inverter output is high.

With reference now to the drawing, in the Figure a cluster of two n-type enhancement node transistors 11 and 12, connected in series to implement the AND function, forms the first stage logic network. A pull-up p-type transistor 13 is connected between the high level V _DD bus of the power source and the output node 14 of the first stage. To serve as the power switch, an n-type pull-down transistor 15 is connected between the low level Vgg bus, typically ground, of the power source (not shown) and the other node 16 of the first logic network. An auxiliary p- type transistor 17 is also connected between the V _DD bus and the output node 14 to trickle continuous charge to node 14. The main pull-up transistor 13 is chosen to have a beta considerably larger, typically a factor of four, than that of the auxiliary pull-up transistor 17 where beta is the ratio of channel width to channel length. The transistors 11 and 12 typically have betas smaller than those of transistor 13 and larger than that of transistor 17. The gate electrodes of transistors 13 and

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15 are connected by way of a bus to a source C of clock pulses while the gate electrode of power switch transistor 17 is connected to the low level bus, or ground. Input information INP is applied to the gate electrodes of the driver transistors 11 and 12.

The second stage of the domino circuit comprises a logic network made up of a cluster of five n-type transistors of which four, 21, 22, 23, and 24, are connected in series to implement an AND function, and the fifth, 25, is connected in shunt across the four to implement the OR function with respect to the four. Additionally, this stage includes its own main and auxiliary pull-up p-type transistors 26,27 and its n-type ground switch pull-down transistor 28. Transistors 26 and 28 are clocked synchronously with transistors 13 and 15. Transistor 27 has its gate electrode tied to ground in the manner of transistor 17. Input information is supplied to the gates of transistors 22, 23, 24 and 25. The gate of transistor 21 is supplied with the output of the first stage by way of the buffer formed by the static CMOS inverter formed by the p-type transistor 29 and the n-type transistor 30 connected in the usual fashion to provide inversion.

In a similar fashion, the third stage comprises a cluster of three n-type transistors 31-33 of which transistors 31,32 are in series to form an AND circuit and transistor 33 is connected in parallel across them to implement the OR function. Pr-type transistors 34 and 35 and n-rtype transistor 36 correspond to transistors 26, 27 and 28 and need no further discussion. Input information is supplied to the gates of transistors 32 and 33 while the gate of transistor 31 is supplied with the output of the second stage by way of the standard static CMOS inverter formed by p-type transistor 37 and n-type transistor 38. Typically there would be additional stages formed by clusters of n-type transistors connected to implement desired logic, and the output available at node 39 would be

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supplied to the gate of one of the transistors in the next stage also by way of a standard CMOS inverter.

The operation of the circuit is readily understood. When the clock is low, all the clocked pull-up p-type transistors conduct and the clocked pull— down n-type transistors are turned off. As a result the output node 14 of the first stage is charged high, essentially to V _DD less the voltage drop experienced across the network formed by transistors 13 and 17. The output nodes 39,40 of the other two stages will similarly be precharged high. The length of the clock pulse should be long enough to ensure that the precharging is complete before the evaluation stage is begun.

At the same time as this precharging is occurring, the input pulses should be applied to the appropriate gates shown by INP of the various driver transistors of the -logic networks. During this time, because of the role of the inverters formed by transistors 29,30 and 37,38 the inputs to the gates of drivers 21 and 31 will be low.

At this point, for evaluation the clock is switched to high, turning off the main pull— up transistors 13, 26 and 34 and turning on the pull-down transistors 15, 28 and 36. Then the conduction state of the various stages will be determined by the states of the input signals applied to the gate electrodes of the various drivers 11, 12, 22, 23, 24, 25, 32, and 33. Drivers 21 and 31 will be supplied with the complements of the outputs at nodes 14 and 40. The presence of transistors 17, 27 and 35 ensures that the precharge voltage on nodes 14, 40 and 39 will remain essentially at the value of V _DD less the small voltage drop associated with transmission through one pull-up network, making the circuit relatively insensitive to noise and leakage effect.

However, it is found that in some instances where the logic network includes a relatively large number of ^■

drivers in series, for example, three or more, that charge sharing may become a problem and that this can be alleviated by the inclusion of other clocked auxiliary pull-up, p-type transistors of small beta to provide current to additional current-shy input nodes of the logic networks.

In particular, in the logic network of the second stage which includes four drivers in series to implement the AND function, an auxiliary pull-up p-type transistor 43 is connected between the high level terminal V _DD bus and the node 44 between drivers 21 and 22, and its gate is connected to the clock terminal. Similarly the auxiliary pull-up, p-type transistor 45 is connected between the high level terminal V _D JJ bus and the node 46 between drivers 22 and 23 and its gate is connected to the clock terminal.

The presence of such transistors ensures that the nodes 44 and 46 are pulled up essentially to V _DD when the clock is low preliminary to the evaluation phase.

It can be appreciated that the clusters of n-type drivers forming each logic network may be interconnected in any manner appropriate to implement the desired logic without affecting the basic operation. In particular the output of any one stage after inversion may be applied simultaneously to more than one driver of other logic networks. For example, it may be supplied to several parallel succeeding stages or even returned additionally to serve as an input in an earlier stage.

It should be apparent that if desired one can use the complementary domino arrangement in which the drivers of the logic networks are p-type enhancement mode transistors and in which the power switch would be a p-type transistor and the precharge network would employ n-type transistors with appropriate change in the polarities of the applied voltages.

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