DIGITAL ARCHITECTURE FOR CONTINUITY TEST

Title:

DIGITAL ARCHITECTURE FOR CONTINUITY TEST

Document Type and Number:

WIPO Patent Application WO/2023/193319

Kind Code:

A1

Abstract:

Efficient continuity testing for instruments connected to a mass interconnect. Digital input and output capabilities may be used on each pin of the mass interconnect to test a variety of input/output (I/O) types on a device under test. Each pin of the interconnect may connect to a respective corresponding digital input and digital output in the tester, with the digital input resistively coupled to the digital output. The connectivity of the pin to the digital input and the digital output, and the connectivity between the digital input and the digital output may be implemented with shift registers and a buffer stage, respectively. In some embodiments, the structure may be implemented through parallel I/O blocks, as in a complex programmable logic device (CPLD), field programmable gate array (FPGA), or microcontroller.

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Inventors:

BRANTLEY BLOCK III ALBERT (US)
THOMAS YARBROUGH III CHARLES (US)
ILIC KOSTA (US)
REN YAOMING (US)

Application Number:

PCT/CN2022/090266

Publication Date:

October 12, 2023

Filing Date:

April 29, 2022

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