[0001] This application claims the priority to Chinese Patent Application No. 201310340789.0, entitled "FIRST-PACKAGED AND LATER-ETCHED THREE-DIMENSIONAL FLIP-CHIP SYSTEM-IN-PACKAGE STRUCTURE AND PROCESSING METHOD THEREFOR", filed with the Chinese Patent Office on August 6, 2013, which is incorporated by reference in its entirety herein.

BACKGROUND

[0002] A conventional quad no-lead metal lead package structure is shown in Figure 98. A processing of manufacturing the metal lead package structure may include: performing a chemical etching and metal plating on a metal sheet to obtain a metal lead frame having pads for carrying chips, and inner and outer pins, and then performing a packaging process such as unilateral die bonding, wire bonding and encapsulating on the metal lead frame.

[0003] Figure 99 shows a conventional organic multiple-layer wiring substrate package structure. A processing of manufacturing the organic multiple-layer wiring substrate package structure may include: stacking a deposited material on a core material of a glass fiber plate in a deposited manner to form a multiple-layer wiring substrate, forming through-holes via the wiring layers by a laser drilling, plating the through-holes to achieve an electric connection, and then performing a packaging process such as unilateral die bonding, wire bonding and encapsulating on the multiple-layer wiring substrate.

[0004] Both of the metal lead frame package structure and the multiple-layer wiring substrate package structure have the following disadvantages.

[0005] 1. Only unilateral chip packaging can be performed on this type of metal lead frame and multiple-layer wiring substrate, thus the metal lead frame or multiple-layer wiring substrate have a low utilization, and a function integration level of whole package is limited.

[0006] 2. No object is embedded into this type of metal lead frame and multiple-layer wiring substrate, thus the metal lead frame and multiple-layer wiring substrate has no functional integration effect, and a function integration level of the whole package is limited. [0007] 3. The organic multiple-layer substrate has high material cost and high manufacturing cost.

[0008] 4. The conventional metal lead frame has great wire width and wire pitch, which is equal to or larger than 200μκι, and thereby the high-density requirement can not be met.

[0009] 5. The conventional organic multiple-layer wiring has a wire width of larger than

I

25μιη and a wire pitch of larger than 25μπι depending on the current etching processing, which are slightly wider in practice.

SUMMARY OF THE INVENTION

[0010] An object of present disclosure is to overcome the disadvantages described above. A

j first-packaged and later-etched flip-chip three-dimensional system-in-package structure and a j processing method thereof are provided. The following problems may be solved: the function integration level of the whole package is limited because a chip and a passive component cannot be embedded into a conventional metal lead frame or a multiple-layer wiring substrate; and compared with the conventional organic substrate, lines with a narrower width and a finer pitch are necessary.

[0011J The object of the present invention may be achieved as follows. A processing method for first-packaged and later-etched a three-dimensional flip-chip system-in-package structure is provided, which includes:

step 1, preparing a metal substrate;

step 2, pre-plating surfaces of the metal substrate with a copper material,

wherein the surfaces of the metal substrate are pre-plated with a layer of copper material; step 3, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on an upper surface and a lower surface of the metal substrate pre-plated with the copper material in step 2;

step 4, removing a part of the photoresist film on the upper surface of the metal substrate, wherein the upper surface of the metal substrate applied with the photoresist film in step 3 is exposed and developed in a pattern by an exposure and development device, to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with a metal wiring layer; step 5, plating with the metal wiring layer,

wherein the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 4, is plated with the metal wiring layer to form pads and pins on the upper surface of the metal substrate;

step 6, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated with the metal wiring layer in step 5;

step 7, removing a part of the photoresist film on the upper surface of the metal substrate, j wherein the upper surface of the metal substrate applied with the photoresist film in step 6 is exposed and developed in a pattern by an exposure and development device, to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with a conductive pillars;

step 8, plating with the conductive pillars,

wherein the region of the upper surface of the metal substrate, on which the part of the photoresist film has been removed in step 7, is plated with the conductive pillars;

step 9, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 10, bonding dies,

wherein a conductive or non-conductive adhesive material is applied on upper surfaces of the pads formed in step 5 to bond first dies;

step 11, bonding metal wires,

wherein the metal wire is bonded between an upper surface of the first die and the pin formed in step 5;

step 12, molding with an epoxy resin,

wherein the upper surface of the metal substrate bonded with the die and the metal wires is molded with the epoxy resin to protect the upper surface of the metal substrate; step 13, grinding a surface of the epoxy resin,

wherein the surface of the epoxy resin is ground after the epoxy resin is molded in step

12;

step 14, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate after the surface of the epoxy resin is ground in step 13;

step 15, removing a part of the photoresist film on the lower surface of the metal substrate,

wherein the lower surface of the metal substrate applied with the photoresist film in step 14 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the lower surface of the metal substrate to be etched;

step 16, etching;

wherein a chemical etching is performed on the region of the lower surface of the metal substrate, on which the part of the photoresist film is removed in step 15;

step 17, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed by softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water;

step 18, plating with an anti-oxidizing metal layer or coating with an antioxidant, wherein the exposed surface of the metal substrate, on which the photoresist film is removed in step 17, is plated with the anti-oxidizing metal layer or is coated with the antioxidant;

step 19, flipping chip;

wherein second dies are flipped, via a metal ball, on a lower surface off the pads and the

i pins, which are plated with the anti-oxidizing metal layer or the coated with the antioxidant, and gaps between metal balls, between the die and the pad, and between the pins are filled with an underfill;

step 20, molding with an epoxy resin,

wherein the lower surface of the metal substrate bonded with the dies is molded with the epoxy resin to protect the lower surface of the metal substrate; and

step 21 , package sawing to form a finished product,

wherein a semi-finished product is sawed after the epoxy resin is molded in step 20j and molded body modules of the metal wiring substrate, which are integrated initially in an array aggregate and contain dies, are sawed to be separated from one another, to form the finished product of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure.

[0012] A processing method for first-packaged and later-etched a three-dimensional flip-chip system-in-package structure is provided, which includes:

step 1, preparing a metal substrate;

step 2, pre-plating surfaces of the metal substrate with a copper material,

wherein the surfaces of the metal substrate are pre-plated with a layer of copper material; step 3, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on an upper surface and a lower surface of the metal substrate pre-plated with the copper material in step 2;

step 4, removing a part of the photoresist film on the upper surface of the metal substrate,

I

wherein the upper surface of the metal substrate applied with the photoresist film in step

3 is exposed and developed in a pattern by an exposure and development device to remove the

j part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with a metal wiring layer;

step 5, plating with the metal wiring layer, wherein the region of the upper surface of the metal substrate, on which the part j of the photoresist film is removed in step 4, is plated with the metal wiring layer to form pads and pins on the upper surface of the metal substrate;

step 6, applying a photoresist film, wherein the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated with the metal wiring layer in step 5;

step 7, removing a part of the photoresist film on the upper surface of the metal substrate, wherein the upper surface of the metal substrate applied with the photoresist film in step 6 is exposed and developed in a pattern by an exposure and development device, to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with conductive pillars;

step 8, plating with the conductive pillars,

wherein the region of the upper surface of the metal substrate, on which the part of the photoresist film has been removed in step 7, is plated with the conductive pillars;

step 9, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 10, bonding dies,

wherein a conductive or non-conductive adhesive material is applied on upper surfaces of the pads formed in step 5 to bond first dies;

step 11, bonding metal wires,

wherein the metal wires are bonded between an upper surface of the first die and the pin

i formed in step 5;

step 12, molding with an epoxy resin,

wherein the upper surface of the metal substrate bonded with the die and the metal wires is molded with the epoxy resin to protect the upper surface of the metal substrate;

step 13, grinding a surface of the epoxy resin,

wherein the surface of the epoxy resin is ground after the epoxy resin is molded in step

12;

step 14, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate after the surface of the epoxy resin has been ground in step 13; step 15, removing a part of the photoresist film on the lower surface of the metal substrate,

wherein the lower surface of the metal substrate applied with the photoresist film in step

14 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the lower surface of the metal substrate to be etched;

step 16, etching;

wherein a chemical etching is performed on the region of the lower surface of the metal substrate, on which the part of the photoresist film is removed in step 15;

step 17, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 18, coating the lower surface of the metal substrate with a solder mask or a sensitive non-conductive adhesive material,

wherein the lower surface of the metal substrate is coated with the solder mask or the sensitive non-conductive adhesive material after the photoresist film is removed in step 17; step 19, exposing and developing to form a window;

wherein the solder mask or the sensitive non-conductive adhesive material on the lower

I

surface of the metal substrate is exposed and developed by an exposure and development device to form the window and expose a region of the lower surface of the metal substrate to be plated with a high conductivity metal layer;

step 20, plating with the high conductivity metal layer,

wherein a region of the window of the solder mask or the sensitive non-conductive adhesive material in step 19 on the lower surface of the metal substrate is plated with the high conductivity metal layer; step 21 , plating with an anti-oxidizing metal layer or coating with an antioxidant, wherein the exposed surface of the metal substrate is plated with the anti-oxidizing metal

i layer or is coated with the antioxidant;

step 22, flipping chips; wherein second dies are flipped, via second metal balls, on tops of the conductive pillars plated with the anti-oxidizing metal layer or coated with the antioxidant in step 21; and gaps between metal balls, and between the die and the conductive pillar may also be filled with an underfill;

step 23, molding with an epoxy resin,

wherein the surface of epoxy resin bonded with the die is molded with the epoxy resin; and

step 24,-package sawing to form a finished product,

wherein a semi-finished product is sawed after the epoxy resin is molded in step 23, and molded body modules of the metal wiring substrate, which are integrated initially in array

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aggregate and contain dies, are sawed to be separated from one another, to form the finished product of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure.

[0013] A processing method for first-packaged and later-etched a three-dimensional flip-chip system-in-package structure is provided, which includes:

step 1, preparing a metal substrate;

step 2, pre-plating surfaces of the metal substrate with a copper material,

wherein the surfaces of the metal substrate are pre-plated with a layer of copper material; step 3, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on an upper surface and a lower surface of the metal substrate pre-plated with the copper material in step 2;

step 4, removing a part of the photoresist film on the upper surface of the metal substrate, wherein the upper surface of the metal substrate applied with the photoresist film in step 3 is exposed and developed in a pattern by an exposure and development device to remoye the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with a first metal wiring layer;

step 5, plating with the first metal wiring layer,

wherein the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 4, is plated with the first metal wiring layer; step 6, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated with the first metal wiring layer in step 5;

step 7, removing a part of the photoresist film on the upper surface of the metal substrate, wherein the upper surface of the metal substrate applied with the photoresist film in step

6 is exposed and developed in a pattern by an exposure and development device to remove the

i part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with a second metal wiring layer;

step 8, plating with the second metal wiring layer,

wherein the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 7, is plated with the second metal wiring layer, and the second metal wiring layer serves as a conductive pillar to connect the first metal wiring layer and a third metal wiring layer;

step 9, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 10, laminating with a non-conductive adhesive film,

wherein a layer of the non-conductive adhesive film is laminated on the upper surface of the metal substrate;

step 11 , grinding a surface of the non-conductive adhesive film,

wherein the surface of the non-conductive adhesive film is ground after the non-conductive adhesive film is laminated in step 10;

step 12, performing a metallization pretreatment on the surface of the non-conductive adhesive film,

of the non-conductive adhesive film; stepl3, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate on which the metallization pretreatment is performed in step 12;

step 14, removing a part of the photoresist film on the upper surface of the metal substrate,

wherein the upper surface of the metal substrate applied with the photoresist film in step 13 is exposed and developed in a pattern by an exposure and development device, to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be etched;

step 15, etching;

wherein the etching is performed on a region of the upper surface of the metal substrate on which the part of the photoresist film is removed in step 14;

step 16, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 17, plating with a third metal wiring layer,

wherein a metallization pretreatment region of the upper surface of the metal substrate reserved by the etching in step 15 is plated with the third metal wiring layer to form a pad and pins on the upper surface of the metal substrate;

step 18, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated with the third metal wiring layer in step 17;

step 19, removing a part of the photoresist film on the upper surface of the metal substrate,

wherein the upper surface of the metal substrate applied with the photoresist film in step

18 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with conductive pillars; step 20, plating with the conductive pillars,

wherein the region of the upper surface of the metal substrate, on which the part of the photoresist film has been removed in step 19, is plated with the conductive pillars;

step 21, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 22, bonding dies,

wherein a conductive or non-conductive adhesive material is applied on upper surfaces of the pads formed in step 17 to bond first dies;

step 23, bonding metal wires,

wherein the metal wire is bonded between an upper surface of the first die and the pin formed in step 17;

step 24, molding with an epoxy resin,

wherein the upper surface of the metal substrate bonded with the die and the metal ^vires is molded with the epoxy resin to protect the upper surface of the metal substrate;

step 25, grinding a surface of the epoxy resin,

wherein the surface of the epoxy resin is ground after the epoxy resin is molded in step

24;

step 26, applying a photoresist film,

wherein the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate after the surface of the epoxy resin is ground in step 25;

step 27, removing a part of the photoresist film on the lower surface of the metal substrate, wherein the lower surface of the metal substrate applied with the photoresist film in step 26 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the lower surface of the metal substrate to be etched;

step 28, etching; wherein a chemical etching is performed on the region of the lower surface of the metal substrate, on which the part of the photoresist film is removed in step 27;

step 29, removing the photoresist film,

wherein the photoresist film on the surface of the metal substrate is removed;

step 30, plating with an anti-oxidizing metal layer or coating with an antioxidant, wherein the exposed surface of the metal substrate, on which the photoresist fihri has been removed in step 29, is plated with the anti-oxidizing metal layer or is coated with the antioxidant;

step 31, flipping chips;

wherein second dies are flipped on a lower surface of the lower surfaces of the pad and

j the pin plated with the anti-oxidizing metal layer or coated with the antioxidant in step 30, by filling gaps between metal balls, between the die and the pad, and between the dies with an underfill;

step 32, molding with an epoxy resin,

wherein the lower surface of the metal substrate bonded with the die is molded with the epoxy resin to protect the lower surface of the metal substrate; and

step 33, package sawing to form a finished product,

wherein a semi-finished product is sawed after the epoxy resin is molded in step 32; and molded body modules of the metal wire substrate, which are integrated initially in j array aggregate and contain dies, are sawed to be separated from one another, to form the finished product of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure.

[0014] Alternatively, during step 5 to step 17 are performed, step 8 to step 18 are performed repeatedly. [0015] A first-packaged and later-etched three-dimensional flip-chip system-in-package structure is provided, which includes: a pad; a pin; a conductive pillar disposed on an upper surface of the pin; a first die flipped on an upper surface of the pad by a conductive or non-conductive adhesive material; a first metal wire for connecting an upper surface of the first die to the upper surface of the pin; a first molding material or epoxy resin for

[0016] Alternatively, a passive device may be connected across the pins.

[0017] Alternatively, a plurality of second dies may be flipped on the lower surfaces of the pad and the pin by filling gaps between metal balls, between the chip and the pad^ and between the chips with an underfill.

[0018] Alternatively, a third die may be flipped on the lower surface of the second die by the conductive or non-conductive adhesive material, and the third die is connected to the lower surface of the pin via a second metal wire. metal ball and the passive device are located within the molding material.

high conductivity metal layers; and an anti-oxidation layer provided on surfaces of the high conductivity metal layers exposed from the solder mask or sensitive non-conductive adhesive material.

[0022] As compared with the prior art, the present disclosure has the following beneficial effects.

[0023] 1. At present, no object can be embedded into the metal lead frame and organic multiple-layer wiring substrate, thus a function integration level of the whole package is limited. In the three-dimensional system-in-package metal wiring substrate provided in the present disclosure, an object can be embedded into an interlayer between the substrates in the manufacturing process, thus chips and other assemblies may be carried on both sides of the three-dimensional system-in-package metal wiring substrate, and the function integration level of the whole package is improved.

[0024] 2. A heat conductive or a heat diffusion object can be embedded into a position or i region of the interlayer of the three-dimensional system-in-package metal wiring substrate in j the manufacturing process as required, and thus the effect of the heat diffusion of the whole package structure is improved.

[0025] 3. An active element, assembly or passive assembly can be embedded into a position j or region of the interlayer of the three-dimensional system-in-package metal wiring substrate in the manufacturing process as required by the system or function, and thus the utilization of substrate is improved.

[0026] 4. The object, which is necessary for system or function and has been embedded into the interlayer, cannot be found from the appearance of the three-dimensional system-in-package metal wiring substrate package finished product. Particularly, the embedding of the silicon chip cannot even be detected by X ray, and thereby the secrecy and protectiveness of the system and function can be achieved fully.

[0027] 5. The three-dimensional system-in-package metal wiring substrate may integrate j with many system functions, thus the space of PCB occupied by the elements with the same function is smaller and the cost is lowered.

[0028] 6. A high voltage device can be embedded into the interlayer of three-dimensional system-in-package metal wiring substrate in the manufacturing process, the high voltage I device and the control chip are respectively provided on two sides of the substrate, ;thus avoiding the interference on the signal transmission due to the heat diffusion of the high voltage device.

[0029] 7. The wiring of the three-dimensional system-in-package metal wiring substrate is manufactured by plating, and the wire width and wire pitch may be smaller than 15μπι.

[0030] 8. The three-dimensional system-in-package metal wiring substrate is manufactured by plating, etching, and molding process, which has a simple process and a lower cost than that of the organic substrate by about 30%.

BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 to Figure 21 are respectively a schematic procedure diagram jof a processing method of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a first embodiment of the present disclosure;

[0032] Figure 22 is a schematic diagram of the first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to the first embodiment of

i the present disclosure;

[0033] Figure 23 to Figure 46 are respectively a schematic procedure diagram of a processing method of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a second embodiment of the present disclosure;

ί

[0034] Figure 47 is a schematic diagram of the first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to the second embodiment of the present disclosure;

[0035] Figure 48 to Figure 92 are respectively a schematic procedure diagram of a processing method of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a third embodiment of the present disclosure;

[0036] Figure 93 is a schematic diagram of the first-packaged and later-fetched three-dimensional flip-chip system-in-package structure according to the third embodiment of the present disclosure;

[0037] Figure 94 is a schematic diagram of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a fourth embodiment of

I

the present disclosure;

[0038] Figure 95 is a schematic diagram of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a fifth embodiment of the present disclosure;

[0039] Figure 96 is a schematic diagram of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a sixth embodiment of the present disclosure;

[0040] Figure 97 is a schematic diagram of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure according to a seventh embodiment of the present disclosure;

[0041] Figure 98 is a schematic diagram of a conventional quad no-lead metal lead package structure; and

[0042] Figure 99 is a schematic diagram of a conventional organic multiple-layer wiring substrate package structure.

[0043] In the drawings:

pad 1

pin 2

conductive pillar 3

first die 4

first metal wire 5

conductive or non-conductive adhesive material 6

underfill 7 second die 8

first molding material or epoxy resin 9

second molding material or epoxy resin 10

anti-oxidation layer 11 high conductivity metal layer 12

solder mask or sensitive non-conductive adhesive material 13

passive device 14

third die 15

second metal wire 16

first metal ball 17

second metal ball 18

DETAILED DESCRIPTION OF THE INVENTION

[0044] A processing method of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure is provided in the present disclosure.

[0045] First embodiment: single-layer wiring, single flip-chip, and lap lead (1)

[0046] Referring to Figure 22, a first-packaged and later-etched three-dimensional flip-chip system-in-package structure is provided in the present disclosure, which includes: a pad 1 ; a pin 2; a conductive pillar 3 provided on an upper surface of the pin 2; a first die 4 flipped on

i an upper surface of the pad 1 by a conductive or non-conductive adhesive material 6; a first metal wire 5 for connecting an upper surface of the first die 4 to the upper surface of the pin 2; a first molding material or epoxy resin 9 for encapsulating with regions of the upper surface of the pad 1 and the pin 2, and a peripheral region of the conductive pillar 3, the first die 4 and the first metal wire 5, with a top of the first molding material or epoxy resin 9 being flush with a top of the conductive pillar 3; an anti-oxidation layer 11 provided on a surface of the conductive pillar 3 exposed from the first molding material or epoxy resin 9; a second die 8 flipped on lower surfaces of the pad 1 and the pin 2 by an underfill 7; and a second molding material or epoxy resin 10 for encapsulating with regions of the lower surfaces of the pad 1 and the pin 2, and a peripheral region of the second die 8.

[0047] The processing method of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure includes the following steps 1 to 21.

[0048] Step 1 , preparing a metal substrate. [0049] Referring to Figure 1, the metal substrate of a suitable thickness is prepared. The metal substrate may be made from copper material, iron material, galvanized material, stainless steel, aluminum material, or metal or nonmetal material which may conduct the electricity. The thickness of the metal substrate may be selected according to the product characteristic.

[0050] Step 2, pre-plating surfaces of the metal substrate with a copper material.

[0051] Referring to Figure 2, the surfaces of the metal substrate are pre-plated with a layer of copper material. The copper layer has a thickness of 2μιη to ΙΟμπι, which may also be thinned or thickened according to the function requirement. The plating may be electrolytic plating, and may also be achieved by chemical deposition.

[0052] Step 3, applying a photoresist film.

[0053] Referring to Figure 3, for manufacturing a metal wiring pattern on the metal substrate later, the photoresist film for exposing and developing is applied on an upper surface and a lower surface of the metal substrate pre-plated with the copper material in step 2j. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0054] Step 4, removing a part of the photoresist film on the upper surface of the metal substrate.

[0055] Referring to Figure 4, the upper surface of the metal substrate applied with the photoresist film in step 3 is exposed and developed in a pattern by an exposure and development device, and the part of the photoresist film in the pattern is removed to expose a region of the upper surface of the metal substrate to be plated with a metal wiring layer.

[0056] Step 5, plating with the metal wiring layer.

electrolytic plating or may be achieved by chemical deposition. [0058] Step 6, applying a photoresist film.

[0059] Referring to Figure 6, for manufacturing conductive pillars later, the photoresist J film for exposing and developing is applied on the upper surface of the metal substrate plated with the metal wiring layer in step 5. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0060] Step 7, removing a part of the photoresist film on the upper surface of the metal substrate.

[0061] Referring to Figure 7, the upper surface of the metal substrate applied with the

I

photoresist film in step 6 is exposed and developed in a pattern by an exposurej and development device, to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with conductive pillars.

[0062] Step 8, plating with the conductive pillars.

[0063] Referring to Figure 8, the region of the upper surface of the metal substrate, on which the part of the photoresist film has been removed in step 7, is plated with the conductive pillars. The conductive pillar may be made from copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium-gold, metal material which may conduct the electricity or the like. The plating may be electrolytic plating, and may achieved by chemical deposition may.

[0064] Step 9, removing the photoresist film.

[0065] Referring Figure 9, the photoresist film on the surface of the metal substrate is removed. The step for removing the photoresist film includes: softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0066] Step 10, bonding dies.

[0067] Referring to 10, a conductive or non-conductive adhesive material is applied on upper surfaces of the pads formed in step 5 to bond first dies.

[0068] Step 11 , bonding metal wires.

[0069] Referring to 11, the metal wires are bonded between an upper surface of the first die and the pins formed in step 5.

[0070] Step 12, molding with an epoxy resin. [0071] Referring to Figure 12, the upper surface of the metal substrate bonded with the die and the wires is molded with the epoxy resin to protect the upper surface of the metal substrate. The epoxy resin material may be selected to be an epoxy with or without filler depending on product characteristic.

[0072] Step 13, grinding a surface of the epoxy resin.

[0073] Referring to Figure 13, the surface of the epoxy resin is ground after the epoxy resin is molded in step 12.

[0074] Step 14, applying a photoresist film.

[0075] Referring to Figure 14, the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate after the surface of the epoxy resin is ground in step 13.

[0076] Step 15, removing a part of the photoresist film on the lower surface of the inetal substrate.

[0077] Referring to Figure 15, the lower surface of the metal substrate applied with the photoresist film in step 14 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the lower surface of the metal substrate to be etched.

[0078] Step 16, etching.

[0079] Referring to Figure 16, a chemical etching is performed in the region of the lower surface of the metal substrate, on which the part of the photoresist film is removed in step 15. The etching method may be an etching process using copper chloride or ferric chloride.

[0080] Step 17, removing the photoresist film.

[0081] Referring to Figure 17, the photoresist film on the surface of the metal substrate is removed, and a step of removing the photoresist film includes softening the photoresist film

I

with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0082] Step 18, plating with an anti-oxidizing metal layer or coating with an antioxidant (organic solderability preservative, OSP).

[0083] Referring to Figure 18, the exposed surface of the metal substrate, on which the

i photoresist film has been removed in step 17, is plated with the anti-oxidizing metal| layer, such as gold, nickel-gold, nickel-palladium-gold or tin, or is coated with the antioxidant (OSP).

[0084] Step 19, flipping chips.

[0085] Referring to Figure 19, multiple second dies are flipped on a lower surface of the pads and the pins plated with the anti-oxidizing metal layer or coated with the antioxidant, by filling gaps between metal balls, between the die and the pad, and between the pads with an underfill.

[0086] Step 20, molding with an epoxy resin.

[0087] Referring to Figure 20, the lower surface of the metal substrate bonded with the dies

j is molded with the epoxy resin to protect the lower surface of the metal substrate. The epoxy

I

resin material may be an epoxy with or without filler depending on the product characteristic.

[0088] Step 21, package sawing to form a finished product.

[0089] Referring to Figure 21, a semi-finished product is sawed after the epoxy resin is molded in step 20, and molded body modules of the metal wiring substrate, which are integrated initially in an array aggregate and contain chips, are sawed to be separated from

i one another, to form the finished product of the first-packaged and later-etched three-dimensional flip-chip system-in-package package structure.

[0090] Second embodiment: single-layer wiring, single flip-chip, and lap lead (2)

mask or sensitive non-conductive adhesive material 13 filled between the high conductivity metal layers 12; and a anti-oxidation layer 11 provided on surfaces of the high conductivity metal layers 12 exposed from the solder mask or sensitive non-conductive adhesive material 13.

[0092] The second embodiment differs from the first embodiment in that, a conductive pillar 3 according to the second embodiment is used actually as an inner lead, and the second

I

molding process is performed on the upper surface of the metal substrate. However, in the

j first embodiment, the conductive pillar 3 is used actually as an outer lead, and the second molding process is performed on the lower surface of the metal substrate.

[0093] The processing method of a first-packaged and later-etched three-dimensional flip-chip system-in-package structure includes the following steps 1 to 24.

[0094] Step 1, preparing a metal substrate.

[0095] Referring to Figure 23, the metal substrate of a suitable thickness is prepared! The

i metal substrate may be made from copper material, iron material, galvanized material, stainless steel, aluminum material or metal material which may conduct the electricity! The thickness of the metal substrate may be selected according to the product characteristic.

[0096] Step 2, pre-plating surfaces of the metal substrate with a copper material.

[0097] Referring to Figure 24, the surfaces of the metal substrate are pre-plated with a | layer of copper material. The copper layer has a thickness of 2μπι to ΙΟμπι, which may also be thinned or thickened according to the function requirement. The plating may be electrolytic plating, and may also be achieved by chemical deposition.

[0098] Step 3, applying a photoresist film.

[0099] Referring to Figure 25, for manufacturing a metal wiring pattern on the metal substrate later, the photoresist film for exposing and developing is applied on an upper surface and a lower surface of the metal substrate pre-plated with the copper material in step 2. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0100] Step 4, removing a part of the photoresist film on the upper surface of the metal substrate.

[0101] Referring to Figure 26, the upper surface of the metal substrate applied with the photoresist film in step 3 is exposed and developed in a pattern by an exposure and development device, and the part of the photoresist film in the pattern is removed to expose a region of the upper surface of the metal substrate to be plated with a metal wiring layer.

0102] Step 5, plating with the metal wiring layer.

chemical deposition.

[0104] Step 6, applying a photoresist film. [0105] Referring to Figure 28, for manufacturing conductive pillars later, the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated j with the metal wiring layer in step 5. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0106] Step 7, removing a part of the photoresist film on the upper surface of the metal substrate.

[0107] Referring to Figure 29, the upper surface of the metal substrate applied with the photoresist film in step 6 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with conductive pillars.

[0108] Step 8, plating with the conductive pillars.

[0109] Referring to Figure 30, the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 7, is plated with the conductive pillars. The conductive pillar may be made from copper, aluminum, nickel, silver,) gold, copper-silver, nickel-gold, nickel-palladium-gold, metal material which may conduct the electricity or the like. The plating may be electrolytic plating, and may also be achieved by chemical deposition.

[0110] Step 9, removing the photoresist film.

[0111] Referring to Figure 31, the photoresist film on the surface of the metal substrate is removed. The step for removing the photoresist film includes: softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0112] Step 10, bonding dies,

[0113] Referring to Figure 32, a conductive or non-conductive adhesive material is applied on upper surfaces of the pads formed in step 5 to bond first dies.

[0114] Step 11, bonding metal wires.

[0115] Referring to Figure 33, the metal wire is bonded between an upper surface of the first die and the pin formed in step 5.

[0116] Step 12, molding with an epoxy resin.

[0117] Referring to Figure 34, the upper surface of the metal substrate bonded with the die and the metal wires is molded with the epoxy resin to protect the upper surface of the metal substrate. The epoxy resin material may be an epoxy with or without filler depending on the product characteristic.

[0118] Step 13, grinding a surface of the epoxy resin.

[0119] Referring to Figure 35, the surface of the epoxy resin is ground after the epoxy resin is molded in step 12.

[0120] Step 14, applying a photoresist film.

[0121] Referring to Figure 36, the photoresist film for exposing and developing is applied

ί on the upper surface and the lower surface of the metal substrate after the surface of the epoxy resin is ground in step 13.

[0122] Step 15, removing a part of the photoresist film on the lower surface of the metal substrate.

[0123] Referring to Figure 37, the lower surface of the metal substrate applied with the photoresist film in step 14 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the lower surface of the metal substrate to be etched.

[0124] Step 16, etching.

[0125] Referring to Figure 38, a chemical etching is performed on the region of the lower surface of the metal substrate, on which the part of the photoresist film is removed in step 15. The method for etching may be an etching process using copper chloride or ferric chloride.

[0126] Step 17, removing the photoresist film.

[0127] Referring to Figure 39, the photoresist film on the surface of the metal substrate is removed by softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0128] Step 18, coating the lower surface of the metal substrate with a solder mask.

[0129] Referring to Figure 40, the lower surface of the metal substrate is coated with the solder mask after the photoresist film has been removed in step 17.

[0130] Step 19, exposing and developing to form a window. conductivity metal layer.

[0132] Step 20, plating with the high conductivity metal layer.

[0133] Referring to Figure 42, a region of the window of the solder mask in step 19 on the lower surface of the metal substrate is plated with the high conductivity metal layer. The plating may be electrolytic plating, and may also be achieved by chemical deposition.

[0134] Step 21, plating with an anti-oxidizing metal layer or coating with an antioxidant (OSP).

[0135] Referring to Figure 43, the exposed surface of the metal substrate is plated with the anti-oxidizing metal layer, such as, gold, nickel-gold, nickel-palladium-gold or tin; or is coated with the antioxidant (OSP).

[0136] Step 22, flipping chips.

[0137] Referring to Figure 44, second dies are flipped, via second metal balls, on tops |of the conductive pillars plated with the anti-oxidizing metal layer or coated with the antioxidant in step 21, and an underfill may be implanted below the flipped second dies to fill gaps between metal balls, and between the chip and a molding material.

[0138] Step 23, molding with an epoxy resin.

[0139] Referring to Figure 45, the surface of epoxy resin bonded with the die is molded jwith the epoxy resin again. The epoxy resin material may be an epoxy with or without filler according to the product characteristic.

[0140] Step 24, package sawing to form a finished product.

[0141] Referring to Figure 46, a semi-finished product is sawed after the epoxy resin is molded in step 23, and molded body modules of the metal wiring substrate, which are integrated initially in a array aggregate and contain chips, are sawed to be separated from one another, to form the finished product of the first-packaged and later-etched three-dimensional flip-chip system-in-package structure.

0142] Third embodiment: multiple-layer wiring, one flip-chip, lap lead

and the pin 2 and a peripheral region of the second die 8.

[0144] The third embodiment differs from the first embodiment in that, a pad 1 and a pin 2 are both formed of multiple metal wiring layers which are connected with each other via a conductive pillar. [0145] The processing method for first-packaged and later-etched a three-dimensional flip-chip system-in-package structure includes the following steps 1 to 45.

[0146] Step 1, preparing a metal substrate.

[0147] Referring to Figure 48, the metal substrate of a suitable thickness is prepared. The metal substrate may be made from copper material, iron material, galvanized material, stainless steel, aluminum material, or metal or nonmetal material which may conduct the electricity. The thickness of the metal substrate may be selected according to the product characteristic.

[0148] Step 2, pre-plating surfaces of the metal substrate with a copper material.

[0149] Referring to Figure 49, the surfaces of the metal substrate are pre-plated with a layer

I

of copper material. The copper layer has a thickness of 2um to ΙΟμπι, which may also be thinned or thickened depending on the function requirement. The plating may be electrolytic plating, and may also be adopted by chemical deposition.

[0150] Step 3, applying a photoresist film.

[0151] Referring to Figure 50, for manufacturing a metal wiring pattern later, the photoresist film for exposing and developing is applied on an upper surface and a lower surface of the metal substrate pre-plated with the copper material in step 2. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0152] Step 4, removing a part of the photoresist film on the upper surface of the metal substrate.

[0153] Referring to Figure 51, the upper surface of the metal substrate applied with the photoresist film in step 3 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a

I

region of the upper surface of the metal substrate to be plated with a first metal wiring layer.

[0154] Step 5, plating with the first metal wiring layer.

[0155] Referring to Figure 52, the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 4, is plated with the first metal wiring layer. The first metal wiring layer may be made from copper, aluminum, nickel, silver! gold, copper-silver, nickel-gold, nickel-palladium-gold, or the like. The plating may be electrolytic plating, and may also be achieved by chemical deposition.

[0156J Step 6, applying a photoresist film.

[0157] Referring to Figure 53, for manufacturing a metal wiring pattern later, the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated

ί with the first metal wiring layer in step 5. The photoresist film may be a dry photoresist; film or a wet photoresist film.

[0158] Step 7, removing a part of the photoresist film on the upper surface of the metal substrate.

[0159] Referring to Figure 54, the upper surface of the metal substrate applied with the photoresist film in step 6 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a

i region of the upper surface of the metal substrate to be plated with a second metal wiring layer.

[0160] Step 8, plating with the second metal wiring layer.

[0161] Referring to Figure 55, the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 7, is plated with the second inetal

I

wiring layer. The second metal wiring layer serves as a conductive pillar to connect the first

j metal wiring layer and a third metal wiring layer. The second metal wiring layer may be made from copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium gold, metal material which may conduct the electricity or the like. The plating may be electrolytic plating, and may also be achieved by the chemical deposition.

[0162] Step 9, removing the photoresist film.

[0163] Referring to Figure 56, the photoresist film on the surface of the metal substrate is removed. The steps for removing the photoresist film includes: softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0164] Step 10, laminating with a non-conductive adhesive film.

[0165] Referring to Figure 57, a region of the upper surface of the metal substrate (with the wiring layer) is laminated with a layer of the non-conductive adhesive film to insulate the first metal wiring layer from the third metal wiring layer. The step for laminating with the non-conductive adhesive film may include: performing the laminating by a conventional rolling device or in a vacuum environment to prevent air from being trapped during the laminating process. The non-conductive adhesive film is mainly a laminated non-conductive adhesive film made from a thermosetting epoxy resin. The epoxy resin may be an epoxy resin with or without filler according to product characteristic.

[0166] Step 11 , grinding a surface of the non-conductive adhesive film.

[0167] Referring to Figure 58, after the non-conductive adhesive film is laminated in step 10, the surface of the non-conductive adhesive film is ground to expose the second metal wiring layer, maintain the flatness of the non-conductive adhesive film and the second metal wiring layer, and control the thickness of the non-conductive adhesive film.

[0168] Step 12, performing a metallization pretreatment on the surface of the non-conductive adhesive film.

drying.

[0170] Stepl3, applying a photoresist film.

[0171] Referring to Figure 60, for manufacturing a metal wiring pattern later, the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the

I

metal substrate on which the metallization pretreatment is performed in step 12. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0172] Step 14, removing a part of the photoresist film on the upper surface of the metal substrate.

[0173] Referring to Figure 61, the upper surface of the metal substrate applied with the photoresist film in step 13 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be etched. [0174] Step 15, etching.

[0175] Referring to Figure 62, a region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 14, is etched to remove a metallization pretreatment region in which the third metal wiring layer is not to be plated. The method for etching may be an etching process using copper chloride or ferric chloride.

[0176] Step 16, removing the photoresist film.

[0177] Referring to Figure 63, the photoresist film on the surface of the metal substrate is removed. The steps for removing the photoresist film includes: softening with the photoresist film a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0178] Step 17, plating with a third metal wiring layer.

[0179] Referring to Figure 64, a metallization pretreatment region of the upper surface of the metal substrate reserved by the etching in step 15 is plated with the third metal wiring layer. The third metal wiring layer may be made from copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium-gold, or the like. The plating may be electrolytic plating, and may also be achieved by the chemical deposition.

[0180] Step 18, applying a photoresist film.

[0181] Referring to Figure 65, for manufacturing a metal wiring pattern later, the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated with the third metal wiring layer in step 17. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0182] Step 19, removing a part of the photoresist film on the upper surface of the metal substrate.

[0183] Referring to Figure 66, the upper surface of the metal substrate pasted with the photoresist film in step 18 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with a fourth metal wiring! layer.

[0184] Step 20, plating with the fourth metal wiring layer.

[0185] Referring to Figure 67, the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 19, is plated with the fourth metal wiring layer. The fourth metal wiring layer serves as a conductive pillar to connect the third metal wiring layer and a fifth metal layer. The fourth metal wiring layer may be made from copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium-gold, metal material which may conduct the electricity or the like. The plating may be electrolytic plating, and may be achieved by the chemical deposition.

[0186] Step 21 , removing the photoresist film.

[0187] Referring to Figure 68, the photoresist film on the surface of the metal substrate is removed. The steps for removing the photoresist film include softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0188] Step 22, laminating with a non-conductive adhesive film.

[0189] Referring to Figure 69, the upper surface of the metal substrate (with the wiring layer) is laminated with a layer of the non-conductive adhesive film to insulate the third metal wiring layer from the fifth metal wiring layer. The step for laminating with the non-conductive adhesive film may include: performing the laminating by a conventional rolling device or in a vacuum environment to prevent air from being trapped during the laminating process. The non-conductive adhesive film is mainly a laminated non-conductive adhesive film made from a thermosetting epoxy resin. The epoxy resin may be an epoxy resin

ί with or without filler depending on the product characteristic.

[0190] Step 23, grinding a surface of the non-conductive adhesive film. layer, and control the thickness of the non-conductive adhesive film.

[0192] Step 24, performing a metallization pretreatment on the surface o!f the non-conductive adhesive film.

[0193] Referring to Figure 71, for providing a conversion intermedium for plating with a metal material later, the metallization pretreatment is performed on the surface of the non-conductive adhesive film to adhere a layer of metallized polymer material onto the surface of the non-conductive adhesive film, or a roughening treatment is performed on the

j surface of the non-conductive adhesive film. The metallized polymer material may be adhered by spraying, plasma oscillation, surface roughening treatment, or the like, and then drying! [0194] Step 25, applying a photoresist film.

[0195] Referring to Figure 72, for manufacturing a metal wiring pattern later, the photoresist

J

film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate on which the metallization pretreatment is performed in step 24. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0196] Step 26, removing a part of the photoresist film on the upper surface of the metal substrate.

[0197] Referring to Figure 73, the upper surface of the metal substrate applied with the photoresist film in step 25 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be etched.

[0198] Step 27, etching.

[0199] Referring to Figure 73, a region of the upper surface of the metal substrate, on which

ί the part of the photoresist film is removed in step 26, is etched to remove a metallization pretreatment region in which the fifth metal wiring layer is not to be plated. The method for etching may be an etching process using copper chloride or ferric chloride.

[0200] Step 28, removing the photoresist film.

[0201] Referring to Figure 75, the photoresist film on the surface of the metal substrate is removed. The steps for removing the photoresist film include softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure yater.

[0202] Step 29, plating with a fifth metal wiring layer.

[0203] Referring to Figure 76, a metallization pretreatment region of the upper surface of the metal substrate reserved by the etching in step 27 is plated with the fifth metal wiring

i layer to form pads and pins on the upper surface of the metal substrate. The fifth metal wiring layer may be made from copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium-gold, or the like. The plating may be electrolytic plating, and may also be achieved by the chemical deposition.

[0204] Step 30, applying with a photoresist film. [0205] Referring to Figure 77, for manufacturing conductive pillars later, the photoresist film for exposing and developing is applied on the upper surface of the metal substrate plated with the fifth metal wiring layer in step 29. The photoresist film may be a dry photoresist film or a wet photoresist film.

[0206] Step 31, removing a part of the photoresist film on the upper surface of the metal substrate.

[0207] Referring to Figure 78, the upper surface of the metal substrate applied with the photoresist film in step 30 is exposed and developed in a pattern by an exposure and development device to remove the part of the photoresist film in the pattern and expose a region of the upper surface of the metal substrate to be plated with the conductive pillars.)

[0208] Step 32, plating with the conductive pillars.

[0209] Referring to Figure 79, the region of the upper surface of the metal substrate, on which the part of the photoresist film is removed in step 31, is plated with the conductive j pillars. The conductive pillar may be made from copper, aluminum, nickel, silver, gold, copper-silver, nickel-gold, nickel-palladium-gold, metal material which may conduct the electricity or the like. The plating may be electrolytic plating, and may also be achieved by the chemical deposition.

[0210] Step 33, removing the photoresist film.

[0211] Referring to Figure 80, the photoresist film on the surface of the metal substrate is removed. The steps for removing the photoresist film include softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0212] Step 34, bonding dies.

[0213] Referring to Figure 81, a conductive or non-conductive adhesive material is applied on upper surfaces of the pads formed in step 29 to bond first dies.

[0214] Step 35, bonding metal wires.

[0215] Referring to Figure 82, the metal wire is bonded between an upper surface of the first die and the pin formed in step 29.

[0216] Step 36, molding with an epoxy resin.

[0217] Referring to Figure 83, the upper surface of the metal substrate bonded with the die and the metal wires is molded with the epoxy resin to protect the upper surface of the metal substrate. The epoxy resin material may be an epoxy resin with or without filler according to the product characteristic.

[0218] Step 37, grinding a surface of the epoxy resin.

[0219] Referring to Figure 84, the surface of the epoxy resin is ground after the epoxy resin is molded in step 36.

[0220] Step 38, applying a photoresist film.

[0221] Referring to Figure 85, the photoresist film for exposing and developing is applied on the upper surface and the lower surface of the metal substrate after the surface of the epoxy resin is ground in step 37.

[0222] Step 39, removing a part of the photoresist film on the lower surface of the metal substrate.

[0223] Referring to Figure 86, the lower surface of the metal substrate applied with the photoresist film in step 38 is exposed and developed in a pattern by an exposure and

I

development device to remove the part of the photoresist film in the pattern and expose a region of the lower surface of the metal substrate to be etched.

[0224] Step 40, etching.

[0225] Referring to Figure 87, a chemical etching is performed on the region of the lower surface of the metal substrate, on which the part of the photoresist film is removed in step 39. The method for etching may be an etching process using copper chloride or ferric chloride.

[0226] Step 41 , removing the photoresist film.

[0227] Referring to Figure 88, the photoresist film on the surface of the metal substrate is removed. The steps for removing the photoresist film includes: softening the photoresist film with a chemical regent or cleaning the surface of the metal substrate with high pressure water.

[0228] Step 42, plating with an anti-oxidizing metal layer or coating with an antioxidant (OSP).

[0229] Referring to Figure 89, the exposed surface of the metal substrate, on which the

j photoresist film is removed in step 41, is plated with the anti-oxidizing metal layer, such as gold, nickel-gold, nickel-palladium-gold or tin; or is coated with the antioxidant (OSP). [0230] Step 43, flipping chips.

[0231] Referring to Figure 90, second dies are flipped on lower surfaces of the pads and the pins plated with the anti-oxidizing metal layer or coated with the antioxidant in step 42, by filling gaps between metal balls, between the die and the pad, and between the pins with an underfill.

[0232] Step 44, molding with an epoxy resin.

[0233] Referring to Figure 91, the lower surface of the metal substrate bonded with the die is molded with the epoxy resin to protect the lower surface of the metal substrate. The epoxy resin material may be an epoxy with or without filler according to the product characteristic.

[0234] Step 45, package sawing to form a finished product.

[0235] Referring to Figure 92, a semi-finished product is sawed after the epoxy resin is molded in step 44; and molded body modules of the metal wire substrate, which are integrated initially in array aggregate and contain chips, are sawed to be separated from one another, to form the finished product of the first-packaged and later-etched three-dimensional flip-chip system-in-package structure.

[0236] Fourth embodiment: single front-mounted chip, lap lead, and a passive device

[0237] Referring to Figure 94, the fourth embodiment differs from the first embodiment in that, a passive device 14 is connected across lower surfaces of pins 2.

[0238] Fifth embodiment: tiled multiple-chip

[0239] Referring to Figure 95, the fifth embodiment differs from the first embodiment in that, multiple second dies 8 are flipped on the lower surfaces of the pads 1 and the pins 2 by the underfill 7.

[0240] Sixth embodiment: multi-tier flip-chip stacked flip-chip

[0241] Referring to Figure 96, the sixth embodiment differs from the first embodiment in that, a third die 15 is front-mounted on the lower surface of the second die 8 by the conductive or non-conductive adhesive material 6, and the third die 15 is connected jto the lower surface of the pin 2 via a second metal wire 16.

[0242] Seventh embodiment: multi-tier flip-chip stacked flip-chip [0243] Referring to Figure 97, the seventh embodiment differs from the first embodiment in that, a third die 15 is flipped on the lower surface of the pin 2 via a second metal ball 1 δ] and the second metal ball 18 and the third die 15 are located within the second molding material or epoxy resin 10.

[0244] The third die 15 may be replaced by a passive device 14. The second metal ball 18 and the passive device 14 are located within the second molding material or epoxy resin 10.