CROSS REFERENCE TO RELATED APPLICATION

[0001]This patent application claims the benefit of U.S. Non-Provisional Patent Application No, 14/574,707, filed on December 18, 2014, which is incorporated by reference in its entirety herein for ail purposes.

BACKGROUND OF THE INVENTION

[0002] Semiconductor power devices have been in use since the early 1950s. They are specialized devices used as switches or rectifiers in power electronics circuits. Semiconductor power devices are characterized by their ability to withstand high voltages and large currents as well as the high temperatures associated with high power operation. For example, a switching voltage regulator will comprise two power devices that constantly switch on and off in a synchronized manner to regulate a voltage. The power devices in this situation need to sink system-level current in the on state, withstand the full potential of the power supply in the off state, and dissipate a large amount of heat. The ideal power device is able to operate in high power conditions, can rapidly switch between on and off states, and exhibits low thermal and on-state resistance.

[0003] A transistor structure referred to as a lateral diffusion metal oxide

semiconductor (LDMOS) can be used to implement a power device. The "lateral diffusion" portion of this term refers to an extension of the drain region that is less strongly doped than the core drain region and that extends laterally away from the channel. This region is often referred to as the low-doped or lightly-doped drain (LDD) region. The LDD region allows the transistor to switch high voltages by making it able to withstand greater voltages in the off-state by absorbing portions of the electric field that would otherwise cause source-drain punch through, and to handle larger currents in the on-state by preventing a large potential drop from building up at the drain-body interface which would otherwise result in degradation of the device via the injection of hot carriers into the body of the device,

[0004] L DM OS transistors can include a gate shield that covers at least a portion of the LDD region and the gate electrode. The gate shield blocks the LDD region and the gate from the large current and voltage signals that are applied to the drain contact of the device. As such, the gate shield lowers the gate-to-drain capacitance of the LDMOS structure. In addition, the gate shield allows for a higher doping of the LDD because the LDD is less affected by large voltage signals applied to the drain contact of the device. As a result, the on-state resistance of the power device can decrease while preserving the device's breakdown and punch-through resistance.

[0005] Figure 1 displays cross section 100 of an LDMOS transistor. The transistor comprises an active region 101 of a semiconductor wafer with an LDD 102 formed therein along with a drain region 103 and source region 104. A channel is formed between LDD 102 and source region 104 under the influence of a voltage applied to gate electrode 105. Gate electrode 105 is separated from the active region by a gate insulator 106. Gate shield 107 is coupled to source contact 108 and shields the gate electrode 105 and LDD 102 from drain contact 109. The source contact 108 of the power device is connected to ground. The gate shield is therefore also biased at ground to provide an adequate shield for LDD 102 and gate electrode 105 without disturbing the carriers in LDD 102. The gate shield is isolated from LDD 102 by an interiayer dielectric 1 10. The interiayer dielectric also provides a surface for additional circuity such as integrated wiring between portions of the same integrated circuit. SUMMARY OF INVENTION

[0006] In one embodiment, a lateral diffusion field effect transistor (LDFET) and an associated control circuit are provided. The embodiment comprises a source region of doped semiconductor material that is electrically coupled to a metallic source contact. The embodiment also comprises a first doped drain region of doped semiconductor material that has a lower dopant concentration than the source region. The embodiment also comprises a second doped drain region of doped semiconductor material that: (1 ) forms an electrically conductive path between the metallic drain contact and the first doped drain region; and (2) has a higher dopant concentration than the first doped drain region. The embodiment also comprises a channel that separates the source region and the first doped drain region. The embodiment also comprises a gate electrode located above the channel and separated from the channel by a gate dielectric. The embodiment also comprises a shield plate located above the gate electrode and the first doped drain region, and separated from the first doped drain region, the gate electrode, and the source contact by an interlayer dielectric. The control circuit applies a variable voltage to the shield plate that: (1 ) pulls majority carriers in the first doped drain region towards the shield plate before the transistor is switched on; and (2) pushes majority carriers in the first doped drain region away from the shield plate before the transistor is switched off.

[0007] In another embodiment, an LDFET and an associated control circuit are provided. The embodiment comprises a source region of doped semiconductor material that is ohmically coupled to a metallic source contact. The embodiment also comprises a first doped drain region of doped semiconductor material that has a lower dopant concentration than the source region, wherein the source region and the first doped drain region have a matching conductivity type. The embodiment also comprises a second doped drain region of doped semiconductor materia! that: (1 ) forms an electrically conductive path between the metallic drain contact and the first doped drain region; (2) has the matching conductivity type; and (3) has a higher dopant concentration than the first doped drain region. The embodiment also comprises a channel that separates the source region and the first doped drain region, wherein the channel has an opposite conductivity type to the matching conductivity type, and wherein the first doped drain region extends at least twice as far from the channel as the source region extends from the channel. The

embodiment also comprises a gate electrode located above the channel and separated from the channel by a gate dielectric, wherein a control voltage applied to the gate electrode controls a flow of current in the channel. The embodiment also comprises a shield plate located above the gate electrode and the first doped drain region, and insulated from the first doped drain region, the gate electrode, and the source contact by an interiayer dielectric. The shield plate is electrically insulated from the gate electrode. The control circuit applies a variable voltage to the shield plate that: (1 ) pulls majority carriers in the first doped drain region towards the shield plate before the transistor is switched on; and (2) pushes majority carriers in the first doped drain region away from the shield plate before the transistor is switched off.

[0008] In another embodiment, an LDFET is provided. The LDFET comprises a source region is electrically coupled to a source contact. The LDFET also comprises a lightly doped drain (LDD) region that has a lower dopant concentration than the source region, and that is separated from the source region by a channel. The LDFET also comprises a highly doped drain region that forms an electrically conductive path between a drain contact and the LDD region. The LDFET also comprises a gate electrode that is located above the channel and that is separated from the channel by a gate dielectric. The LDFET also comprises a shield plate that is located above the gate electrode and the LDD region, and that is separated from the LDD region, the gate electrode, and the source contact by a dielectric layer. The LDFET also comprises a control circuit that applies a variable voltage to the shield plate that: (1 ) accumulates a top layer of the LDD region before the transistor is switched on; and (2) depletes the top layer of the LDD region before the transistor is switched off.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 illustrates a cross section of a lateral diffusion transistor that is in accordance with the related art.

[0010] Figure 2 illustrates a cross section of a lateral diffusion transistor and an accompanying circuit schematic that are in accordance with embodiments of the present invention.

[0011] Figure 3 illustrates a plan view of a lateral diffusion transistor that is in accordance with embodiments of the present invention.

[0012] Figure 4 illustrates a set of waveforms on a single plot charting the drain to source current of a lateral diffusion transistor logarithmically on the y-axis against the drain to source voltage across the lateral diffusion transistor on the x-axis for different voltages applied to the gate shield in accordance with embodiments of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS [0013] Reference now will be made in detail to embodiments of the disclosed invention, one or more examples of which are illustrated in the accompanying drawings. Each example is provided by way of explanation of the present

technology, not as a limitation of the present technology. In fact, it will be apparent to those skilled in the art that modifications and variations can be made in the present technology without departing from the spirit and scope thereof. For instance, features illustrated or described as part of one embodiment may be used with another embodiment to yield a still further embodiment. Thus, if is intended that the present subject matter covers ail such modifications and variations within the scope of the appended claims and their equivalents.

[0014] The lightly doped drain (LDD) region of a lateral diffusion field effect transistor (LDFET) provides the device with an increased breakdown voltage at the expense of increasing the on-resistance of the transistor. Increasing the breakdown voltage of the transistor can be achieved by decreasing the doping level of the LDD or by extending the lateral expanse of the LDD both of which also increase the on- resistance of the device. However, both of these alterations cause a commensurate increase in the on-resistance of the transistor because the impedance of a region of material is directly proportional to the length of the region in the direction of current flow, and because the conductivity of a region of semiconductor material for a particular carrier type is directly proportional to the dopant concentration of a matching conductivity type dopant. This interrelationship presents a difficult design problem because the on-state resistance of a power device must be kept low or the device will burn a significant amount of power when it sinks the large currents that power devices are meant to handle. [0015] The direct trade-off between breakdown voltage and on-resistance can be severed by separately biasing the gate shield of an LDFET transistor with an adaptive voltage that changes based on the state of the device. This approach can be applied to any similar device that includes a lower conductivity region for enhancing breakdown voltages that is shielded from a device contact. For purposes of this disclosure, the LDFET will be applied to describe this family of similar devices. In particular, LDFETs are not limited to devices having metal gate electrodes and oxide gate insulators. The adaptiveiy biased gate shield of an LDFET can still decrease gate to drain capacitance, but it can further serve to decrease the on- resistance of the device while at the same time increasing the breakdown voltage of the device. Instead of being coupled to the source, the gate shield can be connected to a separate control circuit. In some situations, this control circuit is capable of providing a voltage to the gate shield that is less than ground or greater than the supply voltage of the integrated circuit to which it is a part. This bias voltage serves to prevent a build-up of majority carriers in the LDD and thereby combats the effect of a large voltage applied to the drain contact of the device.

[0016] Figure 2 illustrates a semiconductor cross section 200 and an associated circuit schematic 201 that illustrate an approach for improving the on-resistance and voltage hold off of a device over that of an LDFET in which the gate shield is coupled to the source. Cross section 200 includes an LDFET with an active region 202. The active region 202 can be a doped portion of the bulk of a semiconductor wafer, a localized well formed in a larger doped portion of a semiconductor wafer, the active region of a semiconductor-on-insulator (SOI) wafer, or a localized weii formed in an SOI wafer. As illustrated, active region 202 is a thin film formed over the buried insulator 203 of an SOI wafer. [0017] Active region 202 inciudes source region 204, lightly doped drain (LDD) region 205, and drain region 206. All three regions can comprise doped

semiconductor material formed by, for example, the implant of impurities into active region 202. The doped semiconductor material of each region has a similar conductivity type. Therefore, each region can be formed by the same dopant species such as through the implant of one kind of dopant atom. LDD region 205 has a lower dopant concentration than drain region 206 and may also have a lower dopant concentration than source region 204. The LDD region 205 is what provides the LDFET with its superior performance as a power device in terms of its ability to hold off large voltages and not degrade while sinking large currents. The presence of LDD region 205 provides the LDFET with its characteristic of having asymmetric source and drain regions. In some approaches, LDD region 205 generally extends at least twice as far from the channel as the source region extends from the channel. Source region 204 is electrically coupled to source contact 207. Drain region 206 is electrically coupled to drain contact 208. Drain region 206 can be a highly doped drain region and can form an electrically conductive path between drain contact 208 and LDD region 205.

[0018] Source contact 207 and drain contact 208 provide electrical connections to the LDFET from other circuitry which may or may not be integrated with the LDFET on the same integrated circuit. Source region 204 can be electrically coupled to source contact 207 via a silicide layer formed on the surface of source region 204. More generally, source region 204 can be coupled to source contact 207 using any process that forms an ohmic or non-rectifying contact between the two regions of the structure. The connection between drain contact 208 and drain region 206 can comprise any of the variations described above with reference to source contact 207 and source region 204. Source contact 207 and drain contact 208 can comprise a metal, metal alloy, metal siiicide, or an electrically conductive semiconductor material such as doped po!ysi!icon. Exemplary metals, metal alloys, and metal silicides can each comprise copper, tungsten, molybdenum, and aluminum.

[0019] The LDFET in cross section 200 operates as a switch by presenting a variably electrically conductive path from drain contact 208 to source contact 207 through a channel that separates source region 204 and LDD region 205. The channel has an opposite conductivity type to source region 204 and LDD region 205 and separates those two regions from each other. The variability in the conductivity of the electrical path is influenced by a control voltage applied to gate electrode 209 which is separated from the channel by gate dielectric 210. A voltage applied to the gate electrode controls a flow of current in the channel by changing a concentration of free carriers in the channel which thereby creates a localized change in the conductivity type of the channel. From a first order perspective, the LDFET will conduct current when the conductivity type of the localized region matches that of LDD region 205 and source region 204, and will not conduct current when the conductivity type of the localized region is the opposite of that of LDD region 205 and source region 204.

[0020] Shield plate 21 1 is located above gate electrode 209 and LDD region 205, The shield plate can be isolated and separated from the LDD region of the LDFET using an interlayer dielectric that is etched prior to the formation of the shield plate. The same interlayer dielectric can then be formed over the shield plate to isolate it from additional circuity. As illustrated, shield plate 21 1 is separated from LDD region 205, gate electrode 209, and source contact 207 by interlayer dielectric 212. [0021] Shield plate 21 1 is not connected to source contact 207 and is instead electrically isolated from the source. In specific approaches, the gate shield of an LDMOS device is biased by an externally applied voltage. The externally applied voltage can be lower than the voltage applied to the source. These approaches include those in which the source is biased at a ground voltage such that the externally applied voltage is negative. In addition, although cross section 200 has been discussed with reference to an n-channel LDFET in which source region 204 and LDD region 205 have an n-type conductivity, the approaches discussed herein apply to LDFETs of either conductivity type by switching the polarity of the discussed control signals. In this particular instance, for a p-channel LDFET, the shield plate 21 1 could be biased at a voltage in excess of the bias applied to the source region. These approaches include those in which the source is biased at the supply voltage such that the externally applied voltage exceeds the supply voltage.

[0022] The gate shield can be biased via a contact that is formed in various ways. The processing steps used to form the contact can be similar to those used to form source contact 207 and drain contact 208. As illustrated, the contact to gate shield 21 1 is drawn as a vertical contact down through interlayer dielectric 212. However, the contact to gate shield 21 1 does not need to be in the same plane as the channel of the device. Indeed, parasitic capacitance can be decreased in situations where the contact is outside a lateral extent of the LDFET. For example, the gate shield could extend out of the plane of the page to a portion that extends beyond the edge of active region 202, and contact to the gate shield could be formed above that portion of the gate shield. Multiple contacts could also be made to gate shield 21 1 through interlayer dielectric 212 to decrease the impedance of the conductive paths by which each portion of gate shield 21 1 were biased. [0023]The externally applied voltage can be provided by circuity that is integrated on the same integrated circuit as the LDFET or from an external circuit. For example, a charge pump or generic negative voltage generator can be integrated with the LDFET and used to generate the applied voltage. As another example, a control circuit can be formed using standard transistors that are co-integrated with the LDFET. These standard transistors could be complementary metal oxide

semiconductor FETs integrated with the LDFET. An associated control circuit, such as control circuit 201 , could be integrated on a monolithic substrate with the LDFET and could comprise a set of standard complementary FETs. Control circuit 201 could also be part of the same integrated circuit as LDFET cross section 200, but be formed on a separate wafer to form a multi-substrate or 3D integrated circuit.

Likewise, control circuit 201 could be part of the same package as LDFET cross section 200, but be located on a separate die in a multi-die package or 3D package. Although control circuit 201 is illustrated as being formed above cross section 200, this is for illustrative purposes only. The circuit represented by circuit schematic 201 could be formed above cross section 200 on the same monolithic substrate, or it could be formed on another laterally spaced apart portion of the substrate and be connected to the LDFET by a metallization layer above and extending laterally between those two portions of the substrate.

[0024] Control circuit 201 can be set to apply a variable voltage to shield plate 21 1 . The variable voltage can pull majority carriers in LDD region 205 towards shield plate 21 1 before the transistor is switched on and can push majority carriers in LDD region 205 away from shield plate 21 1 before the transistor is switched off. The variable voltage can be different based on the state of the switch. For example, the voltage could vary between different values when the switch was in the on-state, and the channel was providing a conductive path between source contract 207 and drain contact 208, and when the switch was in the off-state, and the channel was not providing a conductive path between source contract 207 and drain contact 208, [0025] Providing a variable voltage to shield plate 21 1 serves to decouple the negative effect of LDD region 205 as to the on-state resistance of the LDFET and the positive effect of LDD region 205 as to the breakdown voltage of the LDFET by making the effective dopant concentration of LDD region 205 variable for a given device. As majority carriers are pulled toward gate shield 21 1 in the on-state, the conductivity of LDD region 205 will increase and the overall conductive path between drain contract 208 and source contract 207 will have lower impedance. As breakdown voltage are relatively not a concern in the on-state, the effective alteration of the dopant concentration towards a higher concentration will not have a deleterious effect on the device. Likewise, as majority carriers are pushed away from shield plate 21 1 in the on-state, the conductivity of LDD region 205 will decrease and the ability of LDD region 205 to prevent hot carrier injection into active region 202 and generally strengthen the LDFET against the application of high voltages will increase. As the conductivity of LDD region 205 is generally not a concern in the off-state, the effective alteration of the dopant concentration towards a lower concentration will not have a deleterious effect on the device.

[0026] The control circuit can vary the voltage applied to the gate shield using various approaches to provide the LDFET performance benefits described above. As illustrated, control circuit 201 includes a control pin 213 and a delayed buffer circuit 214. The signal applied to control pin 213 could match a control signal that would ultimately control gate electrode 209. In these approaches, the delay of the delay buffer could be zero and the control signal would be delayed before being delivered to the gate electrode. In other approaches, control pin 213 may be connected to a sense circuit that measures the amount of current that the LDFET is currently sinking, or will be sinking in the near future, and could linearly adjust the voltage applied to gate shield 21 1 based on the measured current. In situations in which control circuit 201 and LDFET cross section 200 are implemented on the same monolithic substrate, the control pin 213 can provide a connection to circuitry that is external to the integrated circuit or it can provide a connection to other internal circuity on the same monolithic substrate as control circuit 201 .

[0027] Control circuit 201 can ramp the variable voltage between a ground voltage and a supply voltage including ramping the voltage from a negative voltage that is below ground, or from a voltage that is greater than the supply voltage. The ramping of the applied voltage can be conducted based off of the voltage applied to the gate of the LDFET. As mentioned above, the ramp would generally ramp from a negative voltage for the off state of an n-type LDFET and from a voltage greater than the supply voltage for the off state of a p-type LDFET, In particular, the control circuit 201 can ramp the voltage applied to gate shield 21 1 in synchronization with the control signal applied to gate electrode 209.

[0028] As mentioned above, control pin 213 could receive a signal based off of the same control signals used to apply a voltage to gate electrode 209. However, in certain approaches control circuit 201 will begin ramping the voltage applied to the gate shield before the transistor is switched on and complete ramping after the transistor is switched on. In these situations, the signal applied to control pin 213 may need to anticipate the voltage applied to gate electrode 209 such that the voltage applied to gate shield 21 1 would begin ramping before the voltage applied to gate electrode 209 began changing to change the state of the LDFET. Likewise, in certain approaches control circuit 201 will begin ramping the voltage applied to the gate shield 21 1 before the LDFET is switched off and will complete ramping the voltage applied to gate shield 21 1 after the transistor is switched off. In certain approaches, the ramping of the voltage on gate shield 21 1 will be slow enough that it will not ramp to its final level until the state of the LDFET has changed. In other approaches, delay circuit 214 could delay the ramping of the voltage applied to the gate shield to assure that the LDFET had turned completely on before the gate shield bias reached its final value. In other approaches, the delay circuit may include hysteresis such that ramping in one direction was delayed as compared to the other direction. Such approaches would benefit from this hysteresis by not altering the conductivity of LDD region 205 unless the transistor was completely turned on while allowing the conductivity of the LDD region 205 to quickly return to an off-state. This type of approach would protect the transistor in situations where the low impedance state of LDD region 205 was more problematic because breakdown damage can cause irreversible damage to the device as compared to the increase in power consumption and heat generation that would accompany a temporary increase in the on-state resistance of the LDFET.

[0029] Figure 3 illustrates a plan view 300 of the same semiconductor structure illustrated by cross section 200 in Fig. 2. Reference line A is common to both figures. Plan view 300 does not include several layers of the semiconductor structure in order to make lower layers of the structure visible from a plan

perspective. In particular, interlayer dielectric 212 and gate shield 21 1 are not present in plan view 300. The lowest visible layer is active layer 202 which is represented by the rectangle forming the outline of the content of plan view 300. The highest visible layer comprises the conductive material used to form source contact 207 and drain contact 208. Plan view 300 also includes gate electrode 209 and LDD region 205. Plan view 300 also includes two tapered extensions of the gate shield that are outside the plane defined by reference line A such that they are absent from cross section 200. First tapered extension 301 is located on one side of LDD region 205 and its thickest portion is located on the gate side end of LDD region 205. Second tapered extension 302 is located on an opposite side of LDD region 205, but also has its thickest portion located on the gate side end of the LDD region.

[0030] The first and second tapered extensions 301 and 302 are located above the gate electrode and are biased by the externally applied variable voltage such that they are at the same potential as the shield plate. As LDFETs are often distributed in an array pattern on a substrate, the tapered extensions serve to shield the LDD region from adjacent LDFETs. The same decoupling of breakdown voltage and on- state resistance performance is provided by biasing these extensions in the manner described above with reference to the shield plate generally. Tapered extensions 301 and 302 can comprise metal formed above the plane in which the LDD region 205 is formed and can be separated from active region 202 by interlayer dielectric 212. Alternatively, tapered extensions 301 and 302 can be formed in the active region 202 and can comprise regions of heavily doped semiconductor material. In these approaches, the extensions can each be biased using a separate contact formed using the same approaches as discussed above with reference to drain contact 208 and source contact 207. However, the contact can also be formed from the shield plate down to the tapered regions such that it would not be necessary to form an independent contact through interlayer dielectric 212 after the dielectric had been put in place. In other approaches, the first and second tampered extensions 301 and 302 can be coupled to the source of their LDFET or can be connected to a separate externally applied voltage than the gate shield.

[0031] Figure 4 illustrates several waveforms of drain to source voltage against drain to source current for an LDFET on plot 400 having a linear x-axis 401 in units of Volts and a logarithmic y~axis in units of Amperes 402. Waveforms 403, 404, 405, and 406 collectively show how a bias voltage on the gate shield affects the breakdown voltage of an LDFET. All four waveforms show a drain to source current of a negligible 10 pico-Amperes (pA) at a zero volts drain to source voltage. Since the gate bias is at zero volts in ail four waveforms, this is to be expected and shows that each bias condition produces a functional off-state transistor. However, in each case, there is a point where the transistor can no longer hold off a certain drain to source voltage and the transistor breaks. This point is illustrated by a steep vertical portion of the waveform where the transistor is no longer functionally "off" as it is conducting current in the milii-Amperes (mA) range despite having a gate control voltage that should leave the transistor in an off-state.

[0032] Waveforms 403-08 are for an n-channel transistor and have bias voltages applied to the gate shield of 2V, 0V, -1 V, ~2V respectively. As illustrated, the effective breakdown voltage of each device increases as a more negative voltage is applied. Similar results could have been achieved by increasing the length or decreasing the dopant concentration of the LDD. However, as described above, the voltage applied to the gate shield is variable such that the effective ability of the transistor to withstand high breakdown voltage can be applied temporarily and then removed when it again became necessary to have a device exhibiting a low on-state resistance. [0033]Whiie the specification has been described in detail with respect to specific embodiments of the invention, it will be appreciated that those skilled in the art, upon attaining an understanding of the foregoing, may readily conceive of alterations to, variations of, and equivalents to these embodiments. These and other modifications and variations to the present invention may be practiced by those skilled in the art, without departing from the spirit and scope of the present invention, which is more particularly set forth in the appended claims.