METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING SGT

Title:

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING SGT

Document Type and Number:

WIPO Patent Application WO/2015/022744

Kind Code:

A1

Abstract:

In the present invention, SiO2 layers (7aa, 7bb, 7cc, 7dd, 7ee, 7ff) having a circular shape in a planar view are formed by means of isotropic etching using, as masks, SiN layers (8a, 8b, 8c, 8d, 8e, 8f), which are formed on i-layers (5a, 5b) on an i-layer substrate (1), said i-layers having an island-like structure, and which have a rectangular shape identical to that of the i-layers (5a, 5b) in a planar view. Then, the SiN layers (8a, 8b, 8c, 8d, 8e, 8f) are removed, and Si columns (P1-P6) are formed by etching the i-layers (5a, 5b) using the SiO2 layers (7aa, 7bb, 7cc, 7dd, 7ee, 7ff) as masks, then, SGTs (surrounding gate MOS transistors) are formed on the Si columns (P1-P6).

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Inventors:

MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
NAKAMURA HIROKI (JP)

Application Number:

PCT/JP2013/071968

Publication Date:

February 19, 2015

Filing Date:

August 15, 2013

Export Citation:

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Assignee:

UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
NAKAMURA HIROKI (JP)

International Classes:

H01L21/336; H01L21/8238; H01L21/8244; H01L27/092; H01L27/11; H01L29/78

Domestic Patent References:

WO2009096000A1

2009-08-06

Foreign References:

JP2011108702A

2011-06-02

Attorney, Agent or Firm:

KIMURA MITSURU (JP)
Mitsuru Kimura (JP)

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