TERMINATION NOISE IN PROGRAMMABLE DELAY LINES

Patrick Satarzadeh

Jared Zerbe

Barry Daly

FIELD

[0001] The invention relates to variable delay lines for instantiation on integrated-circuit devices.

BACKGROUND

[0002] A delay line imposes a delay on an input signal such that the signal reaches an output of the delay line after a desired lapse of time. Variable delay lines are ubiquitous in integrated circuit technology, and are typically used to phase align related signals. For example, where a data signal is timed to a clock signal, the phases of the clock and data signals may become misaligned due to mismatches between the data and clock paths. In such a case the clock and data can be realigned using a delay line in the clock path, the data path, or both. Similarly, with outbound (transmitted) data the delay line can be used to delay the data signal itself or a clock signal conveyed with the data signal to provide a timing reference. Signal propagation delays vary with integrated-circuit process variables, supply voltage, and temperature, so variable delay circuits are often used to account for such variables.

[0003] Adjustable delay lines come in many forms and are suited to different applications. Some are analog, meaning they can be adjusted by application of an analog control voltage. Others adjust incrementally and are controlled by digital signals. For both types, the performance metrics of interest include the delay adjustment range and noise rejection, and for digital delay lines the granularity of adjustment. Some applications also benefit from a short lead-in delay, which means that the delay line can exhibit a relatively short minimum delay. Unfortunately, these performance metrics are often mutually incompatible.

BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The subject matter disclosed is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:

[0005] Figure 1A depicts a digitally controlled delay circuit 100 in accordance with one embodiment.

[0006] Figure IB is a block diagram of a system 170 illustrating how delay circuit 100 of Figure IB can be used to adjust the delay experienced by one signal to align it with another.

[0007] Figure 2 depicts an embodiment of a digitally controlled delay line 200, or delay circuit, in accordance with another embodiment.

[0008] Figure 3 depicts a delay path 300 in accordance with another embodiment.

[0009] Figure 4 depicts a series of delay elements 400, each of which includes a complementary pair of current-starved inverters 405.

DETAILED DESCRIPTION

[0010] This disclosure describes digitally controlled delay lines (DCDLs) that can be adjusted over a broad range with high resolution, offer relatively low lead-in times, and are relatively insensitive to supply noise. The high resolution allows for finer phase control and the large delay range provides flexibility and facilitates testing.

[0011] Figure 1A depicts a digitally controlled delay circuit 100 in accordance with one embodiment. Delay circuit 100 delays an input signal In on a like-named input node to provide a delayed version of input signal In as output signal Out, also on a like-named node.

Delay circuit 100 includes a delay path 105 and tap-selection circuitry 110. Delay path 105 in turn includes a plurality of variable delay elements 115 coupled in series, the output of one leading to the input of the next. The delay elements for the examples discussed are inverters but can be other logic gates in other embodiments. In this context, a "logic gate" includes at least one active device and performs an operation on one or more inputs. A logic gate can be as simple as an inverter or a buffer gate. The connections between adjacent delay elements 115 provide four delay taps T1-T4. Selection circuit 110 selectively connects one of taps Tl- T4 to output node Out.

[0012] Each delay element 115 includes at least one inverter 120 that exhibits a signal delay. Inverters 120 are symmetrical inverters and are sized to exhibit a minimum logic delay for a given integrated-circuit (IC) process. In this example, let delay increment DI represent the finest delay increment required to meet a desired delay-line resolution, and let the minimum logic delay associated with inverters 120 be two delay increments (2DIs). The minimum non- inverting delay through the two inverters 120 of each delay element 115 is therefore 4DIs. In general, the propagation or logic delay for an optimally sized inverter with a fan-out of one is the minimum logic delay or minimum propagation delay in a given IC process. For the examples which follow, the minimum achievable inverter delay corresponds to a fan-out of two because some of inverters 120 drive both a subsequent inverter 120 and an input to one of multiplexers 140. The inverters 120 shown to have a fan-out of one may additionally drive a dummy load, such as an inverter, to ensure that all inverters 120 have the same fan-out and thus the same delay. Further using a fan-out of two to describe the minimum achievable delay is appropriate for tapped delay lines. Minimum delays are typically expressed as delay ranges to accommodate changes due to process and

environmental variables. The following examples use discrete delay values for ease of illustration, but depending on different manufacturing processes the absolute and relative delay factors for individual elements can change without materially affecting the operation of delay lines in accordance with other embodiments.

[0013] Each inverter 120 exhibits a minimum inverter delay of two delay increments

(2DIs), so the minimum non-inverting delay through the two inverters 120 in each delay element 115 is 4DI. Each delay element 115 additionally includes three switches 125, typically transistors or pass gates, each coupled to a DC terminal (e.g., ground) via a capacitor 130. Each switch 125 connects the output of the respective delay element to the respective capacitor 130 responsive to a control signals C#. The RC time constant of the resulting connection to the DC terminal— a ground node in this example— introduces one delay increment (1DI) in this example. Each delay element 115 can therefore exhibit from four to seven DIs of delay depending on how many switches 125 are turned on. Using input node In as a timing reference point, the output of the leftmost delay element can therefore be delayed by four, five, six, or seven delay increments (i.e., delay D=4,5,6,7). The minimum delay of four is termed Dmin, as shown in a diagram 132 in the lower left corner of Figure 1A.

[0014] Each delay element 115 in this embodiment is similarly adjustable from four to seven DIs in increments of one DI. The delay at tap Tl, the output of the second delay element 115, is the sum of the first two delay elements, and can be set from a minimum of eight DIs (2 x 4DIs) to a maximum of fourteen DIs (2 x 7DIs), in increments of one DI. The numbers between eight and 14 can be achieved using multiple settings in this embodiment. For example, a delay of nine DIs can be obtained by setting the first and second delay elements 115 to four and five, respectively, or vice versa. The granularity of delay adjustment can be different for different delay elements in other embodiments to afford more delay selections. The delay settings are thermometer coded in this embodiment, but other coding schemes, such as binary, can also be used.

[0015] Each subsequent delay tap adds from four to seven additional DIs of delay. Tap T2 can thus be adjusted between twelve and twenty-one (between 3x4 and 3x7), tap T3 between sixteen and twenty-eight (between 4x4 and 4x7), and tap T4 between twenty and thirty-five (between 4x5 and 7x5). [0016] Selection circuit 110, a four- to-one multiplexer in this example, includes three two-to-one multiplexers 140. Multiplexers 140 are tiered in series to minimize the lead-in delay of delay circuit 100. Each multiplexer 140 includes one input coupled to a respective tap. The delay through each multiplexer 140 is assumed to be four DIs in this example, so tap Tl , if selected, produces an output delay range of from twelve to eighteen DIs (D=12-18). The lowest delay value, twelve DI, is the lead-in delay for delay circuit 100 in this example.

[0017] The rightmost multiplexer 140 selects between taps T3 and T4. Because the multiplexer exhibits four DI of delay, selecting tap T3 provides from twenty to twenty-eight DI of delay (D=20-28) and selecting tap T4 provides from twenty-four to thirty-nine (D=24- 39). These ranges overlap, providing a combined delay range D of from twenty to thirty-nine (D=20-39). The center multiplexer 140 likewise introduces four DI of delay and selects between tap T2 and the output from the rightmost multiplexer 140. Selecting tap T2 thus provides from sixteen to twenty-five DI of delay (D= 16-25) and selecting the output of the rightmost multiplexer 140 provides from twenty-four to forty-three (D=24-43). These ranges also overlap, providing a combined delay range of from sixteen to forty-three (D=16-43). Each delay element 115 is identical in this example, though they can be customized to e.g. reduce or eliminate overlapping delay settings.

[0018] The last multiplexer 140 selects either tap Tl or the output from the middle multiplexer 140. These ranges do not overlap in this example, as neither range provides for nineteen DI of delay. The delay imposed on signal In at output node Out can thus span from twelve to eighteen DI or from twenty to forty-seven DIs (D=12-18, 20-47). A single missing incremental value over such a range may not pose a problem in some embodiments and may therefore be tolerated. Even wider gaps may not pose a problem. Such gaps can be closed in other embodiments. For example, the delay from the centermost multiplexer 140, if used as the output, spans the range of from sixteen to forty-three DIs without gaps. The missing delay setting for nineteen DI is thus closed at the expense of an additional four DI of lead-in delay. [0019] An optional multiplexer 150 further illustrates the tradeoff between minimizing the lead-in delay and providing a continuous range of delay settings. Selecting the output from the first delay element 105, considering the four-DI delay imposed by multiplexer 150, leads to a delay range of from eight to eleven (D=8-l 1). The output from node Out likewise delayed provides delay ranges of sixteen to twenty-two and twenty-four to fifty-one (D=16- 22, 24-51). The optional delay range for output node Opt is thus D=8-l 1, 16-22, and 24-51. The resulting relatively low lead-in delay and wide delay range come at the cost of discontinuities in the delay choices (i.e., delays D=12-15 and 23 are not available). The delay elements, delay path, and multiplexing can be adapted to provide a desired delay range and lead-in with or without gaps in the incremental delay value to conform to the needs of a given application. Such adjustments are well within the ability of those skilled in the art in light of this disclosure.

[0020] It may be desired, for some applications, that delay circuit 100 be controlled to increment and decrement responsive to a counter. This behavior can easily be achieved using a look-up table or other logic that maps counts to appropriate settings for control signals C[17:0].

[0021] Figure IB is a block diagram of a system 170 illustrating how delay circuit 100 of Figure IB can be used to adjust the delay experienced by one signal to align it with or deskew it from another. System 170 includes two signal paths Pathl and Path2. Signal path Pathl traverses digitally controlled delay circuit 100 in route to a signal destination 175. Signal path Path2 traverses a fixed delay circuit 180 in route to the same destination 175. Signal destination may be e.g. a latch that captures data delivered on one of paths Pathl and Path2 on clock edges delivered on the other.

[0022] As described above, taking the output of tilted MUX 110 from delay line 100 provides a range of delay adjustment from twelve to forty-seven DI, less a setting for nineteen (i.e., D=12-18 and 20-47). Fixed delay circuit 180 has a delay of about twelve delay increments, in this example, to account for the lead-in delay of delay circuit 100. The combination of delay circuit 100 and the fixed delay 180 can thus compensate for signal skew of from zero to thirty-five delay increments (i.e., from 12-12=0 to 47-12=35, less a setting for 19-12=7).

[0023] Other fixed or variable delays might also be used for path Path2. For example, a fixed delay of thirty DI in path Path2 place edges of the respective signal near the center of the adjustment range for delay line 100. The signal on path Pathl can then be adjusted to lead or lag the signal on path Path2. Delay elements suitable for use as fixed delay circuit 180 are detailed below in connection with Figure 4. In other embodiment signal paths Pathl and Path2 may both traverse an embodiment of delay line 100 to facilitate signal alignment.

[0024] Each delay element introduces undesirable signal jitter, or timing variation, largely a result of power-supply noise. This type of jitter, often referred to as "power-supply- induced jitter" (PSIJ), accumulates from one delay element to the next, growing progressively worse for longer delay settings. Thus, for example, the jitter at node T4 is apt to be greater than that at tap Tl. This may not be a problem for applications with short delay lines, quiet power supplies, or that have relatively high jitter tolerance. However, some high-performance delay-line applications benefit from a highly stable delay line that operates over a considerable range.

[0025] Figure 2 depicts an embodiment of a digitally controlled delay line 200, or delay circuit, in accordance with another embodiment. Delay circuit 200 is in many ways similar to delay circuit 100 of Figure 1 A, like-numbered elements being the same or similar. Delay circuit 200 accommodates longer delays without introducing excessive jitter by incorporating regulated delay elements 205 into the delay path. The regulated delay element 205 lacks the fine, incremental tuning provided by delay elements 115, but limit the buildup of jitter with additional delay stages. The resulting delay circuit can be tailored to optimize the lead-in delay, tuning range, and adjustment granularity without introducing undue phase jitter. Delay circuit 200 is shown to delay an input clock Clk_I to produce an output clock Clk_0, but the delayed signal need not be a clock signal.

[0026] Delay elements 205 each exhibits a delay that is long relative to the unregulated delay element 115, fifteen DIs in this simple example. The regulated delays, if too long relative to the span of delays offered by the adjustable unregulated delay elements, will leave gaps in the delay range provided by delay circuit 200. In the instant example, and again assuming that multiplexers 140 each induce four DIs of delay, control signals C[24:0] can be used to produce a range of delays from sixteen to one hundred three DIs in increments of one DI (i.e., D=16-103).

[0027] Multiplexer 210 is referred to as a "tilted" or "tiered" multiplexer because the constituent 2: 1 multiplexers 140 are coupled in series and in such a way that the tap used to introduce the shortest delay also traverses the shortest path through multiplexer 210. This design facilitates the formation of very short lead-in delays. To produce gap-free delay ranges, multiplexer inputs are selected from nodes that provide enough overlap to accommodate the delay through a single multiplexer 140. For example, the delay elements adjacent to tap Tl can both be controlled to provide delays from sixteen to twenty-one DIs on either tap Tl or tap T2. This six-DI overlap is greater than the four-DI delay through one multiplexer 140, which more than makes up for the additional four-DI multiplexer delay for tap T2. Taps Tl and T2 can thus be selected between without leaving a gap in available delay settings.

[0028] Figure 3 depicts a delay path 300 in accordance with another embodiment. Delay path 300 includes a series of complementary delay element 305, each of which is adjustable in the manner described above in connection with Figure 1 A. Rather than using two inverters to maintain the sense of the input signals, however, delay elements 305 each include just a single inverter stage. The minimum delay associated with each delay state 305 is therefore as short as the minimum logic delay for a given IC process. [0029] Delay path 300 includes complementary taps between adjacent pairs of delay elements 305. The sense of the complementary input signal is maintained by alternating between the two signal paths for successive taps. For example, complementary even taps TapO and /TapO are taken respectively from the upper and lower signal paths, whereas odd taps Tapl and /Tapl are taken respectively from the lower and upper signal paths. The complementary signal from each tap thus maintains the sense of the original input signal. The complementary taps from delay elements 305 are fed into tap selection circuitry 310, in one embodiment a tilted multiplexer similar to selection circuit 110 of Figure 1 A but made up of complementary two-to-one multiplexers. Tap selection circuitry 310 provides complementary output signals Out and /Out on like-named delay-line output nodes in this example, though only one output node may be required for other embodiments. Complementary multiplexers are well known to those of skill in the art, so a detailed discussion of multiplexer 310 is omitted for brevity.

[0030] Figure 4 depicts a series of delay elements 400, each of which includes a complementary pair of current-starved inverters 405. The current through the inverters, and consequently their switching speeds, is governed by bias voltages Vbp and Vpn from a bias- voltage generator 410. These voltages can be adjusted using a digital adjustment signal Adj[2:0] to tailor the delays imposed by the delay elements, to adjust for process and supply- voltage variations for example. Current- starved inverters advantageously suffer lower PSIJ than unregulated delay elements. The requisite bias voltages take time to stabilize at start-up, however, so current- starved inverters take a relatively longer time to become active when waking from a power-down state.

[0031] The architectures described above and in figures shown can be easily

implemented by one skilled in the art using any other type of delay element cell that has controllable incremental delay. Examples of different possible delay cell types include but are not limited to: CML-buffers, CVS and DCVS stages, Domino or Zipper CMOS, and differential CMOS push-pull stages. In some embodiments additional muxing can be incorporated into the delay elements to prevent the delayed signal from propagating past the delay element from which the signal is selected. Preventing the signal from toggling unused delay elements saves power, especially when the delayed signal is a clock that is

continuously toggling. In other embodiments individual delay elements can be powered down by means of series gating of devices to supply rails or to bias devices or any other method well known to those skilled in the art. In some embodiments all elements beyond the currently selected element 'N' will be powered down, whereas in some embodiments all elements beyond 'Ν+ will be powered down to avoid any transient effects from rapidly switching element selection.

[0032] In the foregoing description and in the accompanying drawings, specific terminology and drawing symbols are set forth to provide a thorough understanding of the present invention. In some instances, the terminology and symbols may imply specific details that are not required to practice the invention. For example, circuits described or depicted as including metal oxide semiconductor (MOS) transistors may alternatively be implemented using bipolar technology or any other technology in which a signal-controlled current flow may be achieved.

[0033] An output of a process for designing an integrated circuit, or a portion of an integrated circuit, comprising one or more of the circuits described herein may be a computer-readable medium such as, for example, a magnetic tape or an optical or magnetic disk. The computer-readable medium may be encoded with data structures or other information describing circuitry that may be physically instantiated as an integrated circuit or portion of an integrated circuit. Although various formats may be used for such encoding, these data structures are commonly written in Caltech Intermediate Format (CIF), Calma

GDS II Stream Format (GDSII), or Electronic Design Interchange Format (EDIF). Those of skill in the art of integrated circuit design can develop such data structures from schematic diagrams of the type detailed above and the corresponding descriptions and encode the data structures on computer readable medium. Those of skill in the art of integrated circuit fabrication can use such encoded data to fabricate integrated circuits comprising one or more of the circuits described herein.

[0034] While the present invention has been described in connection with specific embodiments, variations of these embodiments will be obvious to those of ordinary skill in the art. Moreover, some components are shown directly connected to one another while others are shown connected via intermediate components. In each instance the method of interconnection, or "coupling," establishes some desired electrical communication between two or more circuit nodes, or terminals. Such coupling may often be accomplished using a number of circuit configurations, as will be understood by those of skill in the art. Therefore, the spirit and scope of the appended claims should not be limited to the foregoing description. Only those claims specifically reciting "means for" or "step for" should be construed in the manner required under the sixth paragraph of 35 U.S.C. Section 112.