PHASE CHANGE MEMORY AND SEMICONDUCTOR DEVICE

WIPO Patent Application WO/2016/009472

A1

The present invention addresses the problem of providing a phase change memory cell requiring little electric current and electric power to rewrite data. Additionally, the present invention addresses the problem of providing a phase change memory array using said memory cell, consuming little electric power and having good data retaining resistance (retention). An element is made to comprise a first electrode formed on a substrate; a ground layer formed to be in contact with the first electrode, a so-called superlattice layer formed to be in contact with the ground layer, wherein GeTe and Sb2Te3 materials are alternately layered; and a second electrode formed to be in contact with the superlattice layer. Moreover, the direction of the electric current used for the rewriting is specified to go from the ground layer to the superlattice layer. Furthermore, in a memory array constituted using at least two of said memory cells, the second electrodes or wirings electrically short-circuited by the second electrodes electrically short-circuit between all phase change memory cells constituting the memory array.

TAI MITSUHARU (JP)
TAKAURA NORIKATSU (JP)
OOYANAGI TAKASUMI (JP)
KINOSHITA MASAHARU (JP)
MORIKAWA TAKAHIRO (JP)
AKITA KENICHI (JP)

PCT/JP2014/068705

January 21, 2016

July 14, 2014

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HITACHI LTD (JP)

H01L27/105; H01L45/00

JP2014107528A	2014-06-09
JP2010263131A	2010-11-18
JP2010287744A	2010-12-24
JP2007294695A	2007-11-08

SEIRYO I. P. C. (JP)
青稜 patent business corporation (JP)

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