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Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2012/042699
Kind Code:
A1
Abstract:
A semiconductor device provided with a first MIS transistor and a second MIS transistor. The first MIS transistor (nTr1) is provided with: first offset sidewalls (22a) formed on the gate-width-direction side surfaces of a first gate electrode (18a); second offset sidewalls (24a) formed on the gate-length-direction side surfaces of the first gate electrode and on the gate-width-direction side surfaces with the first offset sidewalls interposed therebetween; and a first extension region (26a). The second MIS transistor (nTr2) is provided with: third offset sidewalls (22b) formed on the gate-length-direction side surfaces and gate-width-direction side surfaces of a second gate electrode (18b); fourth offset sidewalls (24b) formed on the gate-length-direction side surfaces and gate-width-direction side surfaces of the second gate electrode with the third offset sidewalls interposed therebetween; and a second extension region (23b).

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Inventors:
MORIYAMA YOSHIYA
Application Number:
PCT/JP2011/001998
Publication Date:
April 05, 2012
Filing Date:
April 04, 2011
Export Citation:
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Assignee:
PANASONIC CORP (JP)
MORIYAMA YOSHIYA
International Classes:
H01L21/8234; H01L27/088
Foreign References:
JP2006294877A2006-10-26
JP2007273816A2007-10-18
JP2009140967A2009-06-25
Attorney, Agent or Firm:
MAEDA, Hiroshi et al. (JP)
Hiroshi Maeda (JP)
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