Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2009/069365
Kind Code:
A1
Abstract:
Provided is a highly integrated switching resistive RAM having a short readout
time. An NPN type bipolar transistor (BT) has an N well (11) as a collector layer,
a P+ type Si layer (12A) formed on the surface of the N well (11) as a base layer, and
an N+ type Si layer (15) formed on the surface of the P+ type Si layer (12A) as an emitter
layer. A word line (WL0) is electrically connected to the N+ type Si layer (15),
and bit lines (BL1-BL4) intersect with the word line (WL0). Furthermore, a plurality
of switching layers (14) are formed on the surface of the P+ type Si layer (12A)
and electrically connected to the corresponding bit lines for performing switching
between the on-state and the off-state, and a potential fixing line (19A) fixes
the P+ type Si layer (12A) at a prescribed potential.
Inventors:
SUDA YOSHIYUKI (JP)
OTA YUTAKA (JP)
OTA YUTAKA (JP)
Application Number:
PCT/JP2008/066500
Publication Date:
June 04, 2009
Filing Date:
September 08, 2008
Export Citation:
Assignee:
SANYO ELECTRIC CO (JP)
SANYO SEMICONDUCTOR CO LTD (JP)
UNIV TOKYO NAT UNIV CORP (JP)
SUDA YOSHIYUKI (JP)
OTA YUTAKA (JP)
SANYO SEMICONDUCTOR CO LTD (JP)
UNIV TOKYO NAT UNIV CORP (JP)
SUDA YOSHIYUKI (JP)
OTA YUTAKA (JP)
International Classes:
H01L27/10; G11C13/00; H01L45/00
Foreign References:
| JP2004158863A | 2004-06-03 | |||
| JPH11345485A | 1999-12-14 | |||
| JP2002367365A | 2002-12-20 | |||
| JPH06275791A | 1994-09-30 | |||
| JP2005538552A | 2005-12-15 | |||
| JP2006313912A | 2006-11-16 |
Attorney, Agent or Firm:
SUTO, Katsuhiko (388 Komaigi-cho,Ota-sh, Gunma 18, JP)
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