Title:
SIGNAL PROCESSING CIRCUIT AND RECEPTION DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/062770
Kind Code:
A1
Abstract:
The present invention reduces the clock frequency required for the generation of local signals in a harmonic rejection mixer. An N-1 (where N is an even number greater than 2) number of converters convert high-frequency signals to N-1 sets of current signals that each have a certain amplitude. A local signal generation unit comprises an N number of flip-flops connected in a ring configuration. The local signal generation unit generates N-1 sets of local signals. An N-1 number of mixers respectively mix N-1 sets of current signals and N-1 sets of local signals. An N number of flip-flops output, without change and in accordance with a mode signal, signals input to some of the flip-flops.
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Inventors:
YOSHIKAWA NAOTO (JP)
ARIMA MARI (JP)
ARIMA MARI (JP)
Application Number:
PCT/JP2021/038033
Publication Date:
April 20, 2023
Filing Date:
October 14, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03D7/00
Domestic Patent References:
| WO2016125600A1 | 2016-08-11 |
Foreign References:
| JP2004179841A | 2004-06-24 | |||
| JP2012060319A | 2012-03-22 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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