SINGLE PULSE MAGNETO-STRICTIVE SWITCHING VIA HYBRID

MAGNETIZATION STACK

BACKGROUND

[0001] Spintronics is the study of intrinsic spin of the electron and its associated magnetic moment in solid-state devices. Spintronic logic are integrated circuit devices that use a physical variable of magnetization or spin as a computation variable. Such variables can be non-volatile (i.e., preserving a computation state when a power to an integrated circuit is switched off). Non-volatile logic can improve the power and computational efficiency by allowing architects to put a processor to un-powered sleep states more often with less energy. Existing spintronic logic generally suffer from high energy and relatively long switching times.

[0002] For example, large write current (e.g., greater than ΙΟΟμΑ) and voltage (e.g., greater than 0.7V) are needed to switch a magnet (i.e., to write data to the magnet) in Magnetic Tunnel Junctions (MTJs). Existing Magnetic Random Access Memory (MRAM) based on MTJs also suffer from high write error rates (WERs) or low speed switching. For example, to achieve lower WERs, switching time is slowed down which degrades the performance of the MRAM. MTJ based MRAMs also suffer from reliability issues due to tunneling current in the tunneling dielectric of the MTJs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0004] Fig. 1 illustrates an arrangement of four electrodes to apply in-plane electric field for magneto-strictive switching.

[0005] Fig. 2 illustrates a hybrid magnetization stack operable to switch by magnetostriction, according to some embodiments of the disclosure.

[0006] Fig. 3 illustrates a hybrid magnetization stack operable to switch by magnetostriction, according to some other embodiments of the disclosure.

[0007] Figs. 4A-B illustrate plots showing magneto-strictive operation using the hybrid magnetization stack, according to some embodiments of the disclosure. [0008] Fig. 5A illustrates a hybrid magnetization stack operable to switch by magnetostriction, according to some embodiments of the disclosure.

[0009] Fig. 5B illustrates a hybrid magnetization stack operable to switch by magnetostriction, according to some other embodiments of the disclosure.

[0010] Fig. 6 illustrates a memory bit-cell formed using hybrid magnetization stack operable to switch by magneto-striction, according to some embodiments of the disclosure.

[0011] Fig. 7 illustrates a hybrid magnetization stack with Spin Orbit Coupling (SOC) material and is operable to switch by magneto-striction, according to some embodiments of the disclosure.

[0012] Fig. 8 illustrates a hybrid magnetization stack with SOC material and is operable to switch by magneto-striction, according to some embodiments of the disclosure.

[0013] Fig. 9 illustrates a memory bit cell with a hybrid magnetization stack, according to some embodiments of the disclosure.

[0014] Fig 10 illustrates a flowchart of a method for operating the hybrid magnetization stack using magneto-striction, according to some embodiments of the disclosure.

[0015] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-Chip) with hybrid magnetization stack operable to switch by magneto-striction, according to some embodiments.

DETAILED DESCRIPTION

[0016] Fig. 1 illustrates an arrangement 100 of four electrodes to apply in-plane electric field for magneto-strictive (MS) switching. The four electrodes are labeled as two 'A' electrodes and two 'B' electrodes. In this example, MS switching is achieved by applying an in-plane electric field through a first set of electrodes and then applying another in-plane electric field through a second set of electrodes. Image 101 of arrangement 100 shows the case when 0.5V is applied to the first set of electrodes 'A' while no voltage is applied to the second set of electrodes 'B.' Once the magnetization is defined by the MS effect, 0.5V is applied to the second set of electrodes 'B' while no voltage is applied to the first set of electrodes 'A' as shown by image 102 of arrangement 100. As such, MS switching occurs.

[0017] This process of MS switching is challenging to manufacture because special fabrication steps are needed to apply an in-plane electric field. Further, to apply an in-plane electric field, large voltage is needed which increases power consumption. The MS switching process for arrangement 100 is also slow because it is at least a two-step switching process that requires a minimum number of four spatially separated electrodes.

[0018] Some embodiments described here use a hybrid nano-magnet with both perpendicular magnetization and in-plane magnetic anisotropy. Anisotropy generally refers to a material property which is directionally dependent. Anisotropy for a magnet can come from the shape of the magnet and/or from the magnetic anisotropy of the magnetic material due to crystalline anisotropy or interface anisotropy in multi-layered stacks. For in-plane magnets, shape anisotropy is determined by the shape of the magnet. Magnets tend to align along the long axis of the shape. Anisotropy is characterized by the associated effective magnetic field Hk. Materials with high magnetic field Hk are materials with properties that are highly directionally dependent.

[0019] For in-plane magnets, shape anisotropy typically corresponds to modest values of Hk, for example, 500-600 Oersted (Oe). Out-of-plane magnets with Perpendicular Magnetic Anisotropy (PMA) have a higher magnetic field Hk than in-plane magnets, and the anisotropy of the PMA magnet does not have a strong correlation with its shape. As such, PMA magnets can be square or round shaped (as opposed to rectangular shaped in-plane magnets) and can achieve faster switching with lower currents than in-plane magnets.

[0020] In some embodiments, the hybrid nano-magnet has two stable states— an out-of-plane PMA stable state and an in-plane stable state. As such, the hybrid nano-magnet of some embodiments can be used for storing and reading data. In some embodiments, the out-of- plane stable state is a result of thickness and magneto-crystalline anisotropy caused by an application of strain to a MS ferromagnet (FM). In some embodiments, the in-plane stable state is a result of exchange coupling or bias from a synthetic anti-FM. In some

embodiments, a layer exhibiting Spin Orbit Coupling (SOC) is deposited over the layer of MS FM.

[0021] There are many technical effects/benefits of various embodiments. For example, the hybrid nano-magnet of various embodiments allows for voltage controlled magnetization switching that has intrinsically lower energy to switch compared to current induced spin torque switching. The drive currents present during transients are also significantly lower in the hybrid nano-magnet of the various embodiments than the spin torque switching currents. The hybrid nano-magnet of the various embodiments reduce critical current/voltages to improve the reliability of the switching devices. Other technical effects will be apparent from the description of the various embodiments and the figures. [0022] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0023] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0024] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The term "circuit" or "module" may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0025] The terms "substantially," "close," "approximately," "near," and "about," generally refer to being within +/- 10% of a target value (unless specifically specified). Unless otherwise specified the use of the ordinal adjectives "first," "second," and "third," etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0026] For the purposes of the present disclosure, phrases "A and/or B" and "A or B" mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and/or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C). [0027] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors— BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The term "M " indicates an n-type transistor (e.g., NMOS, NPN BJT, etc.) and the term "MP" indicates a p-type transistor (e.g., PMOS, PNP BJT, etc.).

[0028] Fig. 2 illustrates a hybrid magnetization stack 200 (also referred to as the hybrid nano-magnet) which is operable to switch by MS, according to some embodiments of the disclosure. In some embodiments, hybrid magnetization stack 200 comprises piezo-electric (PZe) or Ferro-electric (FE) layer 201, MS FM layer 202 (also referred to as MS FM1), tunneling barrier layer (e.g. MgO) 203, a fixed magnet FM2 204, Anti-FM layers 205a and 205b, and electrodes 207a, 207b, and 207c. In some embodiments, hybrid magnetization stack 200 further comprises a layer 206 of templating material for Anti-FM 205b.

[0029] In some embodiments, PZe or FE layer 201 is operable to exert strain on MS FM1 202 in response to voltage Vstrain applied across PZe or FE layer 201 via electrodes 207a/b. The range of voltage Vstrain is in the range of 30mV to 300mV, in accordance with some embodiments. In some embodiments, PZe or FE layer 201 is formed of: PZT (e.g., Pb(Zro.2 Tio.8)03); BaTi03, or CoFeO. In other embodiments, other materials may be used for forming PZe or FE layer 201. For example, materials such as PZT-5, PZT-4, PZNPT, PMNPT, BiFe03; Bi ₄ Ti30i2; Polyvinylidene fluoride, and PVDF can be used for forming PZe or FE layer 201.

[0030] In some embodiments, electrode 207a is coupled to PZe layer 201 and to Anti-FM layer 205a. In some embodiments, electrode 207b is coupled to PZe layer 201. Electrodes 207a/b can be made of any non-magnetic conducting material such as Cu. In some embodiments, a voltage source (not shown) is coupled to electrodes 207a/b to apply voltage Vstrain across PZe layer 201. In some embodiments, the voltage source applies one of a +Vstrain voltage, -Vstrain voltage, or no voltage across electrodes 207a/b.

[0031] In some embodiments, MS FM1 layer 202 (i.e., ferromagnetic layer with magneto- strictive property) is deposited over PZe layer 201. In some embodiments, MS FM1 layer 202 is formed of materials such as: Teffenol-D; Fei- _x Ga _x ; Coo.6Feo. ₄ ; or CoFe20 ₄ (CFO). In other embodiments, other materials that exhibit change in preferred magnetic anisotropy axes as a function of applied strain to the structure may be used for forming MS FM1 layer 202. For example, iFe20 ₄ and Metglas® 2605 (e.g., Fe8iB13.5Si3.5C2 and FesoB ₂ o) magnetic alloy may be used for forming MS FM1 layer 202.

[0032] In some embodiments, MS FM1 layer 202 comprises a multi-layered perpendicular stack of materials. For example, MS FM1 layer 202 comprises a stack such as layers of Cobalt and Platinum (i.e., Co/Pt). Other examples of the multiple layers include: Co/Pd; Co/Ni; MgO/ CoFeB/Ta/ CoFeB/MgO; MgO/CoFeB/W/CoFeB/MgO;

MgO/ CoFeB/V / CoFeB/MgO; MgO/CoFeB/Mo/CoFeB/MgO; Mn _x Ga _y ; Materials with L10 crystal symmetry; or materials with tetragonal crystal structure.

[0033] In some embodiments, Anti-FM layer 205a is deposited over PZe layer 201 such that Anti-FM layer 205a is sandwiched between PZe layer 201 and MS FM1 layer 202. In some embodiments, Anti-FM layer 205a acts on the free magnetic layer of MS FM1 layer 202 to set an in-plane magnetization direction in MS FM1 layer 202. In some embodiments, Anti- FM layer 205a can be formed of materials such as PtMn, IrMn, PdMn, and FeMn. In some embodiments, tunneling barrier layer 203 is deposited over MS FM1 layer 202. In some embodiments, tunneling barrier layer 203 is formed of MgO.

[0034] In some embodiments, a layer of FM2 204 is deposited over tunneling barrier layer 203. In some embodiments, FM2 layer 204 is fixed in-plane magnet. In some embodiments, FM2 layer 204 is formed of CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, FM2 layer 204 is formed with high spin polarization materials. Heusler alloys are an example of high spin polarization materials. Heusler alloys are ferromagnetic because of double-exchange mechanism between neighboring magnetic ions.

[0035] In some embodiments, FM2 layer 204 is formed with a sufficiently high anisotropy (Hk) and sufficiently low magnetic saturation (M _s ) to increase injection of spin currents. Magnetic saturation M _s is generally the state reached when an increase in applied external magnetic field H cannot increase the magnetization of the material (i.e., total magnetic flux density B substantially levels off). Here, sufficiently low M _s refers to M _s less than 200 kA/m (kilo-Amperes per meter). Anisotropy Hk generally refers to the material property which is directionally dependent. Materials with high Hk are materials with material properties that are highly directionally dependent. Here, sufficiently high Hk in context of Heusler alloys is considered to be greater than 2000 Oe (Oersted).

[0036] In some embodiments, Heusler alloys such as Co2FeAl and Co2FeGeGa are used for forming FM2 layer 204. Other examples of Heusler alloys include: Cu ₂ MnAl, Cu2MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa, Co ₂ MnAl, Co ₂ MnSi,

Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Fe ₂ Val, Mn ₂ VGa, Co ₂ FeGe, etc.

[0037] In some embodiments, a layer of Anti-FM layer 205b is deposited over FM2 layer 204. In some embodiments, Anti-FM layer 205b layer is formed of a material where spins directions alternate in crystal planes so it cannot be switched by magnetic field of spin torque. In some embodiments, Anti-FM layer 205b layer pins the adjacent ferromagnetic layer (i.e., does not allow the adjacent FM layer to switch to an opposite direction). In some

embodiments, Anti-FM layer 205b layer can be formed of materials such as PtMn, IrMn, PdMn, and FeMn.

[0038] In some embodiments, templating layer 206 is formed over Anti-FM layer 205b to enhance the crystallinity of Anti-FM layer 205b. In some embodiments, transition metals such as Ag and Cu are used for forming templating layer 206. In some embodiments, templating layer 206 is formed of one of: Ru, Ta, W, or a thin layer of MgO. In some embodiments, electrode 207c is formed over templating layer 206. In some embodiments, a resistance sensor that senses the resistance across hybrid magnetization stack 200 is coupled to electrodes 207a and 207c. In some embodiments, the sensor is a current sensor to sense current through the stack when Vsense is applied across electrodes 207a/c. In other embodiments, other types of sensors may be used to determine the memory state of hybrid magnetization stack 200.

[0039] In some embodiments, bit-line (BL) is coupled to electrode 207c. In some embodiments, a transistor is coupled to electrode 207a such that the transistor is controlled by word-line (WL) and one of its source/drain terminals is coupled to electrode 207a while the other drain/source terminal is couple to a first source-line (SL1). In some embodiments, electrode 207b is coupled to a second SL (SL2). [0040] In some embodiments, to write to hybrid magnetic device 200, voltage Vstrain is applied across electrodes 207a and 207b. The applied voltage turns the magnetization of MS FMl 202 by 90° degrees, in accordance with some embodiments. In some embodiments, to read from hybrid magnetic device 200, sense voltage Vsense is applied across electrodes 207a and 207c, and current is measured through hybrid magnetic device 200. This current measures the magnetoresistance of hybrid magnetic device 200. High resistance may represent a logic high and low resistance may represent a logic low, or vice versa. The relative resistance (i.e., high resistance or low resistance) depends on the magnetizations of MS FMl layer 202 and FM2 layer 204, in accordance with some embodiments.

[0041] Fig. 3 illustrates hybrid magnetization stack 300 operable to switch by MS, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 3 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such, hybrid magnetization stack 300 is described with reference to Fig. 2. Compared to hybrid magnetization stack 200, in hybrid magnetization stack 300, MS FM layer 202 (which is relabeled here as MS FMl 302) is extended over Anti-FM layer 205a (which is relabeled here as Anti-FM layer 305a). In some embodiments, electrode 207a (relabeled as electrode 307a) is formed over MS FMl layer 302. One technical benefit of hybrid magnetization stack 300 is that more uniform strain is provided by PZe layer 201 to MS FMl layer 302.

[0042] Figs. 4A-B illustrate plots 400 and 420, respectively, showing the MS operation using hybrid magnetization stack 200, according to some embodiments of the disclosure. It is pointed out that those elements of Figs. 4A-B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. While Figs. 4A-B are described with reference to the operation of hybrid magnetization stack 200, the same explanation applies to hybrid magnetization stack 300 and other hybrid stacks of various embodiments.

[0043] In some embodiments, the operation of hybrid magnetization stack 200 is verified using Landau-Lifshitz-Gilbert simulations. In the following description, PZe or FE layer 201 is PZT (i.e., tetragonal mono-domain ferroelectric, Pb(Zr0.2Ti0.8)O3) which is a film grown on a conducting bottom electrode 207b. In some embodiments, MS FMl layer 202 is lithographically patterned. In some embodiments, Vstrain is applied across electrodes 207a/b to generate an in-plane bi-axial strain in PZe or FE layer 201, which is transferred to MS FMl layer 202. [0044] In this example, for PZe or FE layer 201 (i.e., PZT film) with (xyz=001) surface orientation (i.e., ferroelectric polarization along the ±z-axis), the bi-axial strain is equal in magnitude and sign along the in-plane crystallographic directions, (xyz=010) and (xyz=100). The strain components along the (xyz=010) and (xyz=100) directions are given by:

where, d ₃₁ is the piezoelectric coefficient of PZe or FE layer 201. On the other hand, for PZT with (110) surface orientation, the application of an out-of-plane electric field (from Vstrain) creates two different strains along the two in-plane crystallographic directions, (001) and (101). In such a case, it can be shown that the strain components ε _χχ along the (001) and (101) directions are given by:

^E xx ⁼ (d ₃₁ + d ₃₃ - j= . . . (2)

and

½ ^{= £} yy ⁼ ^3 l ^ · · · (3)

respectively.

[0045] The following section analyzes the response of MS FMl layer 202 to a stress pulse. In the presence of a bi-axial stress, the magnetic anisotropy of MS FMl layer 202 changes due to the inverse magneto-striction effect. The energy contribution E _strain due to the stresses, {oi}, (i≡xx,y) making angles, and {5i} with the unit vector along the direction of the magnetization is given by:

where, λ is the magnetostrictive coefficient of the magnetic material. In this example, MS FMl 202 is formed of Coo.6Feo.4, which has a large magnetostrictive coefficient. Assuming the complete transfer of strain from PZe or FE layer 201 to MS FMl 202, the stress and the strain in MS FMl 202 are related by:

oi =Y& (i≡ xx,yy) . . . (5)

where, Ύ' is the Young's modulus of the magnetic material.

[0046] The total energy E _total of the magnet with a perpendicular magnetic anisotropy (PMA) H _k upon the application of a biaxial stress is given by:

Etotai ⁼ EPMA + E _strain = -μ ₀ Μ ₅ Ηΐι sin Θ + E _strain . . . (6) where, E _PMA , M _s , μ ₀ , and Θ are the energy of the magnet with PMA, saturation magnetization of the magnet, the vacuum permeability, and the angle of the magnetization with respect to the -z axis, respectively. [0047] The anisotropy field due to the stress is calculated using the following relation:

distrain

^H ° - ^~ Ί Γ ^{■■■ {Ί} >

[0048] The dynamics of the nanomagnet of MS FM1 layer 202 is described by the modified Landau-Lifshitz-Gilbert equation, which is as follows:

dm _r — > → , , Γ— > dfn \ , I _v

— = -γμ ₀ [m x H _eff ] + a [m x -j + - . . . (8) where, γ is the electron gyromagnetic ratio, a is the Gilbert damping coefficient, l _p is the component of the vector spin current perpendicular to the magnetization fn entering the nanomagnets, and N _s is the total number of Bohr magnetons per magnet.

[0049] Here,

H _e ff = Η _σ + H _PMA + H _N . . . (9)

is the effective magnetic field and H _PMA and H _N are the fields due to perpendicular magnetic anisotropy and stochastic noise, respectively.

[0050] The noise field:

H _N = H _i ii + H _j y + H _fc z . . . (10)

acts isotropically on the magnet of MS FM1 layer 202 and hence can be described as:

<H _I (t)> = 0 . . . (l l)

(H^H^t')) = ¾¾ «S(t - t')S _lk . . . (12) where, kB is the Boltzmann constant, T is the temperature, and V is the volume of the nanomagnets of MS FM1 202.

[0051] In order for the initial conditions of the magnets to be randomized, the initial angle of the magnets follows the relationship:

[0052] In some embodiments, the magnetization dynamics of the nanomagnet of MS FM1 layer 202 is simulated in the presence of a uniform bi-axial stress, σ(= σ _χχ = a _yy ). In order to understand the steady state condition of the magnet of MS FM1 layer 202 under the effect of the uniform bi-axial stress, equation 6 indicates that without an applied stress (i.e., σ = 0), the total energy is the minimum along ±z-axis (θ=0° and 180°). For a uniform bi-axial stress, σ, the stress energy can be written as:

Estrain = CO S ² Θ . . . (14)

[0053] Hence, with the increase of the bi-axial stress, the anisotropy energy along the ±z-axis increases and above a critical stress: . . . (15)

3λ

θ =90° (the xy -plane) becomes the minimum energy plane. Assuming the continuity of strain at the interface between the nanomagnet of MS FM1 layer 202 and the underlying PZe or FE layer 201, the voltage V _PE (same as Vstrain) required across PZe or FE layer 201 to generate the stress is given by:

where d _PE is the thickness of PZe or FE layer 201.

[0054] The magneto-strictive switching of hybrid magnetic stack 200 is illustrated by Fig. 4A. Here, x-axis is time (in nanoseconds) and y-axis is spin projection. Plot 400 shows three regions— 401, 402, and 403. Section 401 illustrates the out-of-plane direction of

magnetization of MS FM1 layer 202 in the absence of Vstrain (i.e., Vstrain=0V). Section 402 illustrates the direction of magnetization of MS FM1 layer 202 when Vstrain is exerted on PZe or FE layer 201. Vstrain, through MS, causes the out-of-plane stable state to change to in-plane stable state. Section 403 illustrates the out-of-plane direction of magnetization of MS FM1 layer 202 in the absence of Vstrain (i.e., Vstrain=0 or -Vstrain). Each of the sections— 401, 402, and 403 illustrates the state states of MS FM1 layer 202.

[0055] The stable magnetic directions of hybrid magnetization stack(s) 200/300 are shown in Fig. 4B. In some embodiments, hybrid magnetization stack 200/300 has a magnetic anisotropy that can be stable out-of-plane or in-plane when no electric-voltage is applied to the stack. In this disclosure, the embodiments are described with reference to a stable in- plane magnetic anisotropy state when no voltage is applied across PZe or FE layer 201. However, MS FM1 layer 202 can be designed such that it has a stable out-of-plane magnetic anisotropy state when no voltage is applied across PZe or FE layer 201.

[0056] In some embodiments, MS FM1 layer 202 within hybrid magnetization stack 200 is stabilized in-plane via exchange field applied from the synthetic anti-ferromagnet or from the natural anti-ferro-magnet. In some embodiments, MS FM1 layer 202 within hybrid magnetization stack 200 is stabilized out-of-plane via strain tunable perpendicular anisotropy originating from crystalline or interface PMA. Switching of hybrid magnetization stack 200/300 under applied voltage shows reversible magnetic switching from in-plane to PMA and vice- versa. In some embodiments, the state of MS FM1 layer 202 is non-volatile when the voltage is removed. In some embodiments, the steady state of MS FM1 layer 202 is either along the +/-z direction or +x direction in-plane. In some embodiments, this magnetization of MS FM1 layer 202 within hybrid magnetization stack 200 can be read via Rashba effect and/or TMR (tunnel magnetoresistance) effect.

[0057] Fig. 5A illustrates hybrid magnetization stack 500 operable to switch by magnetostriction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5A having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig. 5A and Fig. 2 are described.

[0058] In some embodiments, instead of PZe layer 201 coupling to MS FM1 layer 202 via Anti-FM layer 205a, additional layers are sandwiched between PZe layer 201 and MS FM1 layer 202. In some embodiments, FM bias layer 501 is deposited over Anti-FM layer 205a. In some embodiments, FM bias layer 501 is a non-MS layer. In some embodiments, FM bias layer 501 is formed of any of the materials discussed with reference to FM2 layer 204.

[0059] In some embodiments, an exchange coupling or bias layer 502 of Ru, Cu, or Ag is deposited over FM bias layer 501 such that exchange coupling or bias layer 502 is sandwiched between MS FM1 layer 202 and FM bias layer 501 (which is a non-MS layer). In some embodiments, exchange coupling or bias layer 502 comprises of Ru, Cu, or Ag which can allow for tunneling of spin electron wave-function to allow for RKKY (Ruderman- Kittel-Kasuya-Yosida) exchange coupling. RKKY exchange coupling refers to a coupling mechanism of nuclear magnetic moments or localized inner 'd' or 'f shell electron spins in a metal by means of an interaction through the conduction electrons. In other embodiments, other materials may be used for forming exchange coupling or bias layer 502 that have an appropriate thickness for wave-function overlap leading to ferromagnetic/anti-FM coupling.

[0060] One technical effect of FM bias layer 501 is that is exerts exchange interaction that breaks the inversion symmetry and sets a preferred in-plane direction for magnetization of MS FM1 202. The role of exchange coupling or bias layer 502 is to mediate the exchange interaction, which is a strongly varying function of the thickness of layer 502, in accordance with some embodiments. The operation of hybrid magnetization stack 500 is otherwise similar to the operation of hybrid magnetization stack 200, in accordance with some embodiments.

[0061] Fig. 5B illustrates hybrid magnetization stack 520 operable to switch by magnetostriction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 5B having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, differences between Fig. 5A, Fig. 5B, and Fig. 3 are described.

[0062] Compared to hybrid magnetization stack 300, instead of PZe layer 201 coupling to MS FM1 layer 302 via Anti-FM layer 305a, additional layers are sandwiched between PZe layer 201 and MS FM1 layer 302. In some embodiments, FM bias layer 521 is deposited over Anti-FM layer 305a. In some embodiments, FM bias layer 521 is a non-MS layer. In some embodiments, FM bias layer 521 is formed of any of the materials discussed with reference to FM bias layer 501. In some embodiments, an exchange coupling or bias layer 522 of Ru, Cu, or Ag is deposited over FM bias layer 521 such that exchange coupling or bias layer 521 is sandwiched between MS FM1 layer 302 and FM bias layer 521 (which is a non- MS layer). In some embodiments, exchange coupling or bias layer 522 is formed of any of the materials discussed with reference to exchange coupling or bias layer 502.

[0063] Fig. 6 illustrates memory bit-cell 600 formed using hybrid magnetization stack operable to switch by magneto-striction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 6 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0064] In some embodiments, bit-cell 600 comprises bit-line (BL), first source-line (SL1), second SL (SL2), access transistor (e.g., n-type transistor M 1), and hybrid magnetization stack 601 (e.g., one of 200, 300, 500, and 520). In some embodiments, the source/drain terminal of access transistor M 1 is coupled to electrode 207a/307a, the drain/source terminal of the access transistor M 1 is coupled to SL1, and the gate terminal of the access transistor M 1 is coupled to word-line (WL). In some embodiments, SL2 is coupled to electrode 207b. In some embodiments, BL is coupled to electrode 207c. While the embodiment of Fig. 6 is described with reference to an n-type access transistor, in some embodiments the access transistor can be replaced with a p-type transistor.

[0065] In some embodiments, to write a logic state as a non-volatile state to bit-cell 600, Vstrain or write voltage is applied across electrodes 207a/307a and 207b. In some

embodiments, the applied Vstrain or write voltage causes the magnetization of MS FM1 layer 202 of hybrid magnetization stack 601 to switch (or turn) by 90° degrees. For example, if the first stable magnetization state of MS FM1 layer 202 (when no Vstrain is applied) is out-of- plane relative to the surface of the wafer, then applying Vstrain or write voltage across electrodes 207a/307a and 207b causes the magnetization of MS FM1 layer 202 to switch to in-plane relative to the surface of the wafer. In some embodiments, SL2 is grounded (i.e., electrode 207b is coupled to VSS), and voltage is applied to electrode 207a/307a by turning on access transistor MN1 and applying voltage on SL1 to electrode 207a/307a. By switching the magnetization of MS FM1 layer 202, a logic state is stored in bit-cell 600.

[0066] In some embodiments, to read the logic state stored in bit-cell 600, a sensor (not shown) is used to measure the magnetoresistance of hybrid magnetization stack 601. In some embodiments, to measure the magnetoresistance of hybrid magnetization stack 601, voltage Vsense is applied across electrodes 207c and 207a/307a and current is measured through hybrid magnetization stack 601. For example, BL is selected for activating bit-cell 600 (i.e., Vsense is applied on electrode 207c), WL is raised to turn on the access transistor M 1, and SL1 is coupled to ground.

[0067] The current sensed by the sensor (not shown) indicates the magnetoresistance of hybrid magnetization stack 601. The magnetoresistance of hybrid magnetization stack 601 depends on the direction of magnetizations of FM2 layer 204 relative to MS FM1 layer 202. If the directions of magnetizations of FM2 layer 204 and MS FM1 layer 202 are the same (e.g., in-plane) then the resistance is lower than when the directions of magnetizations of FM2 layer 204 and MS FM1 layer 202 are different (e.g., when the magnetization of FM2 layer 204 is in-plane while the magnetization of MS FM1 202 is out-of-plane). A low resistance may indicate a state of logic low in bit-cell 600 while a higher resistance may indicate a state of high in bit-cell 600.

[0068] Fig. 7 illustrates hybrid magnetization stack 700 with Spin Orbit Coupling (SOC) material and is operable to switch by magneto-striction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 7 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 7, Fig. 7 is described with reference to Fig. 2.

[0069] In some embodiments, the layers above MS FM1 layer 302 are replaced with a SOC layer 701. SOC layer 701 is a layer that is operable to exhibit spin Hall effect (SHE). In some embodiments, electrode 207c is deposited on one end of SOC layer 701. In some embodiments, another non-magnetic conductor 707d (e.g., a conductor formed from Cu) is coupled in series with SOC layer 701. [0070] In some embodiments, SOC layer 701 is made of one or more of β-Tantalum (β-Ta), Ta, β-Tungsten (β-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. In some embodiments, SOC layer 701 transitions into high conductivity non-magnetic metal(s) 707d to reduce the resistance of SOC layer 701. In some embodiments, non-magnetic metal 707d is formed from one or more of: Cu, Co, a-Ta, Al, CuSi, or Si.

[0071] In some embodiments, spin-to-charge conversion is achieved by SOC layer 701 via spin orbit interaction in metallic interfaces (i.e., using Inverse Rashba-Edelstein Effect (IREE) and/or Inverse SHE (ISHE), where a spin current injected from an input magnet produces a charge current.

[0072] Table 1 summarizes transduction mechanisms for converting spin current to charge current and charge current to spin current for bulk materials and interfaces.

Table 1: Transduction mechanisms for Spin to Charge and Charge to Spin Conversion using SOC

[0073] In some embodiments, SOC layer 701 comprises layers of materials exhibiting inverse spin orbit coupling (ISOC) such as one of inverse SHE (ISHE) or inverse Rashba- Edelstein effect (IREE). In some embodiments, SOC layer 701 comprises a stack of layers with materials exhibiting IREE and ISHE effects. In some embodiments, SOC layer 701 comprises a metal layer, such as a layer of Copper (Cu), Silver (Ag), or Gold (Au), which is coupled to MS FM1 layer 302. In some embodiments, the metal layer is a non-alloy metal layer.

[0074] In some embodiments, SOC layer 701 also comprises layer(s) of a surface alloy, e.g. Bismuth (Bi) on Ag coupled to the metal layer. In some embodiments, the surface alloy is a templating metal layer to provide a template for forming MS FM1 layer 302. In some embodiments, the metal of the metal layer which is directly coupled to MS FM1 layer 302 is a noble metal (e.g., Ag, Cu, or Au) doped with other elements for group 4d and/or 5d of the Periodic Table.

[0075] In some embodiments, the surface alloy is one of: Bi-Ag, Antimony-Bismuth (Sb-Bi), Sb-Ag, Lead-Nickel (Pb-Ni), Bi-Au, Pb-Ag, Pb-Au, β-Ta; β-W; Pt; or Bi ₂ Te ₃ . In some embodiments, one of the metals of the surface alloy is an alloy of heavy metal or of materials with high SOC strength, where the SOC strength is directly proportional to the fourth power of the atomic number of the metal.

[0076] Here, the crystals of Ag and Bi of SOC layer 701 have lattice mismatch (i.e., the distance between neighboring atoms of Ag and Bi is different). In some embodiments, the surface alloy is formed with surface corrugation resulting from the lattice mismatch, (i.e., the positions of Bi atoms are offset by varying distance from a plane parallel to a crystal plane of the underlying metal). In some embodiments, the surface alloy is a structure not symmetric relative to the mirror inversion defined by a crystal plane. This inversion asymmetry and/or material properties lead to spin-orbit coupling in electrons near the surface (also referred to as the Rashba effect).

[0077] In some embodiments, when the spin current s from MS FM1 layer 302 flows through the 2D (two dimensional) electron gas between Bi and Ag in SOC layer 701 with high SOC, charge current I _C is generated. In some embodiments, the interface surface alloy of BiAg2/PbAg2 of SOC layer 701 comprises of a high density 2D electron gas with high Rashba SOC. The spin orbit mechanism responsible for spin-to-charge conversion is described by Rashba effect in 2D electron gases. In some embodiments, 2D electron gases are formed between Bi and Ag, and when current flows through the 2D electron gases, it becomes a 2D spin gas because as charge flows, electrons get polarized.

[0078] The Hamiltonian energy HR of the SOC electrons in the 2D electron gas

corresponding to the Rashba effect is expressed as:

H _R = a _R (k x ζ). σ . . . (3)

where a _R is the Rashba coefficient, 'k' is the operator of momentum of electrons, z is a unit vector perpendicular to the 2D electron gas, and σ is the operator of spin of electrons.

[0079] The spin polarized electrons with direction of polarization in-plane (in the xy -plane) experience an effective magnetic field dependent on the spin direction which is given as:

^B ( ^k = ¾ ^ ^X ) - - - (4)

where ^ _B is the Bohr magneton.

[0080] This results in the generation of a charge current in the interconnect proportional to the spin current I _s . The spin orbit interaction at the Ag/Bi interface (i.e., the Inverse Rashba- Edelstein Effect (IREE)) produces a charge current l _c in the horizontal direction which is expressed as:

l _c = . . . (5) where w _m is width of the magnet, and λ _ΙΚΕΕ is the IREE constant (with units of length) proportional to a _R .

[0081] The IREE effect produces spin-to-charge current conversion around 0.1 with existing materials at lOnm magnet width. For scaled nanomagnets (e.g., 5nm width) and exploratory SHE materials such as Bi2Se3, the spin-to-charge conversion efficiency can be between 1 and 2.5, in accordance with some embodiments. The net conversion of the drive charge current l _d to magnetization dependent charge current is:

where P is the spin polarization.

[0082] The charge current I _c then propagates through non-magnetic interconnect 707d coupled to SOC layer 701. In some embodiments, non-magnetic interconnect 707d is coupled to BL.

[0083] Fig. 8 illustrates hybrid magnetization stack 800 with SOC material and is operable to switch by magneto-striction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 8 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments of Fig. 8, Fig. 8 is described with reference to Fig. 2, Fig. 5, and Fig. 7.

[0084] In some embodiments, the layers above MS FM1 layer 302 are replaced with a SOC layer 701 and associated electrodes 207c and 707d as described with reference to Fig. 7. In some embodiments, instead of just Anti-FM (AFM) layer 305a being sandwiched between MS FM1 layer 302 and PZe layer 201, FM bias layer (i.e., a non-MS layer) 521, AFM layer 305a, and layer of Ru 522 is sandwiched between MS FM1 layer 302 and PZe layer 201 as described with reference to Fig. 5. Operation wise, hybrid magnetization stack 800 operates similarly to hybrid magnetization stack 700, in accordance with some embodiments.

[0085] Fig. 9 illustrates memory bit-cell 900 formed using hybrid magnetization stack 700/800 operable to switch by magneto-striction, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 9 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiment of Fig. 9, Fig. 9 is described with reference to Fig. 6.

[0086] In some embodiments, bit-cell 900 comprises BL, SL1, SL2, access transistor (e.g., n- type transistor M 1), and hybrid magnetization stack 901 (e.g., one of 700 or 800). In some embodiments, the source/drain terminal of access transistor MNl is coupled to electrode 207a/307a, the drain/source terminal of the access transistor MNl is coupled to SLl, and the gate terminal of the access transistor MNl is coupled to WL. In some embodiments, SL2 is coupled to electrode 207b. In some embodiments, BL is coupled to electrode 707d. While the embodiment of Fig. 9 is described with reference to an n-type access transistor, in some embodiments the access transistor can be replaced with a p-type transistor.

[0087] In some embodiments, to write a logic state as a non-volatile state to bit-cell 900, Vstrain or write voltage is applied across electrodes 207a/307a and 207b. In some

embodiments, the applied Vstrain or write voltage causes the magnetization of MS FM1 layer 202 of hybrid magnetization stack 901 to switch (or turn) by 90° degrees. For example, if the first stable magnetization state of MS FM1 layer 202 (when no Vstrain is applied) is out-of- plane relative to the surface of the wafer, then applying Vstrain or write voltage across electrodes 207a/307a and 207b causes the magnetization of MS FM1 layer 202 to switch to in-plane relative to the surface of the wafer. In some embodiments, SL2 is grounded (i.e., electrode 207b is coupled to VSS), and voltage is applied to electrode 207a/307a by turning on access transistor MNl and applying voltage on SLl to electrode 207a/307a. By switching the magnetization of MS FM1 layer 202, a logic state is stored in bit-cell 900.

[0088] In some embodiments, to read the logic state stored in bit-cell 900, a sensor (not shown) is used to measure the charge current I _c flowing on BL 707c. In some embodiments, to measure the charge current I _c flowing on BL 707c, voltage Vsense is applied across electrodes 707c and 207a/307a while electrode 207c is grounded, and current is measured through hybrid magnetization stack 901. For example, BL is selected for activating bit-cell 900 (i.e., Vsense is applied on electrode 707c), WL is raised to turn on the access transistor MNl, and SLl and electrode 207c are coupled to ground.

[0089] The direction of current sensed by the sensor (not shown) indicates the magnetization of FM. The direction of the charge current produced by SOC layer 701 depends on the direction of magnetization of MS FM1 302. In some embodiments, if the current on BL is flowing out of hybrid magnetization stack 901, then the logic stored is logic 1. In some embodiments, if the current on BL is flowing into hybrid magnetization stack 901, then the logic stored is logic 0.

[0090] Fig. 10 illustrates flowchart 1000 of a method for operating the hybrid magnetization stack 200/300/500/520 using MS, according to some embodiments of the disclosure. It is pointed out that those elements of Fig. 10 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0091] Although the blocks in the flowchart with reference to Fig. 10 are shown in a particular order, the order of the actions can be modified. Thus, the illustrated embodiments can be performed in a different order, and some actions/blocks may be performed in parallel. Some of the blocks and/or operations listed in Fig. 10 are optional in accordance with certain embodiments. The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks must occur.

Additionally, operations from the various flows may be utilized in a variety of combinations.

[0092] At block 1001, a first voltage is applied across a layer (i.e., PZe or FE layer 201) which is operable to exert strain on a first FM layer (i.e., MS FM1 layer 202/302). The applied first voltage changes the magnetization of FM1 layer 202/303 by MS. In this example, the magnetization becomes out-of-plane from in-plane.

[0093] At block 1002, a second voltage Vsense across the first FM layer 202/302 and Anti-FM layer 205a is applied and current through the stack is sensed via a sensor (not shown). The sensed current determines the logic state stored in the stack. Depending on the resistance of hybrid magnetization stack 200/300/500/520, which is determined by the magnetization of FM2 layer 204 layer and MS FM1 layer 202/302, the memory state of hybrid magnetization stack 200/300/500/520 is determined.

[0094] For example, when both FM2 layer 204 and MS FM1 layer 202 have in-plane magnetizations in the same direction, the resistance of hybrid magnetization stack 200 is lower resistance, and when FM2 layer 204 has in-plane and MS FM1 layer 202 has out-of- plane magnetizations, the resistance of hybrid magnetization stack 200 is higher. Higher resistance may represent storing of logic 1 and lower resistance may represent storing of logic 0, of visa versa.

[0095] At block 1003, the first voltage is removed or made negative to remove strain on first FM layer 202. As such, MS FM1 layer 202 regains its native stable state. In this example, that state is the in-plane stable state. In some embodiments, the magnet of MS FM1 layer 202 is captured in in-plane direction due to the exchange force of Anti-FM layer 205 a described above. In some embodiments, MS FM1 layer 202 is switched back to in-plane by applying a second voltage (e.g., 0V or -Vstrain). While the flowchart of Fig. 10 is described with reference to Fig. 2, flowchart 1000 is also applicable to other hybrid magnetization stacks (e.g., stack 300, 500, and 520), in accordance with some embodiments. [0096] Fig. 11 illustrates a smart device or a computer system or a SoC (System-on-Chip) with hybrid magnetization stack (e.g., 200, 300, 500, 520, 700, and 800) operable to switch by magneto-striction, according to some embodiments. It is pointed out that those elements of Fig. 11 having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0097] Fig. 11 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart- phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[0098] In some embodiments, computing device 1600 includes first processor 1610 with hybrid magnetization stack operable to switch by magneto-striction, according to some embodiments discussed. Other blocks of the computing device 1600 may also include hybrid magnetization stack operable to switch by magneto-striction, according to some

embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[0099] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[00100] In some embodiments, computing device 1600 includes audio subsystem

1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610.

[00101] In some embodiments, computing device 1600 comprises display subsystem

1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[00102] In some embodiments, computing device 1600 comprises I/O controller 1640.

I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[00103] As mentioned above, I O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[00104] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features). [00105] In some embodiments, computing device 1600 includes power management

1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[00106] Elements of embodiments are also provided as a machine-readable medium

(e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00107] In some embodiments, computing device 1600 comprises connectivity 1670.

Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00108] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00109] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00110] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00111] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00112] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00113] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00114] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00115] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00116] For example, an apparatus is provided which comprises: a first ferromagnetic

(FM) layer with magneto-strictive (MS) property; a first anti-FM layer coupled directly or indirectly to the first FM layer; and a piezo-electric (PZe) layer coupled to the first anti-FM layer. In some embodiments, the apparatus comprises: a first electrode coupled to a surface of the PZe layer and to the first anti-FM layer; and a second electrode coupled to another surface of the PZe layer. In some embodiments, the apparatus comprises a voltage source, coupled to the first and second electrodes.

[00117] In some embodiments, the apparatus comprises: a first electrode coupled to the first FM layer; and a second electrode coupled to another surface of the PZe layer. In some embodiments, the apparatus a voltage source, coupled to the first and second electrodes. In some embodiments, the first FM layer is formed of at least one of: Terfenol-D (Tb _x Dyi- _x Fe2); Fei xGa _x ; Coo.6Feo. ₄ ; or CoFe20 ₄ . In some embodiments, the PZe layer is operable to exert strain on the first FM layer.

[00118] In some embodiments, the PZe layer is formed of at least one of: Pb(Zro.2

Tio.8)0 ₃ ; PbTiCh; BaTiOs; BiFeO,; BI4TI3O12: Polyvinylidene fluoride; or PMNPT. In some embodiments, the apparatus comprises: a tunneling barrier layer deposited over the first FM layer; and a second FM layer deposited over the tunneling barrier layer. In some

embodiments, the tunneling barrier layer is formed of MgO. In some embodiments, the apparatus comprises a second anti-FM layer coupled to the second FM layer. In some embodiments, the apparatus comprises a templating layer coupled to the second anti-FM layer.

[00119] In some embodiments, the first and second anti-FM layers are formed of at least one of: PtMn; IrMn; PdMn; or FeMn. In some embodiments, the first FM layer is operable to have an out-of-plane magnetization direction relative to magnetization direction of the second FM layer when strain is exerted on the first FM layer, and wherein the magnetization direction of the second FM layer is in-plane. In some embodiments, the first FM layer is operable to have an in-plane magnetization direction relative to magnetization direction of the second FM layer when strain is removed from the first FM layer, and wherein the magnetization direction of the second FM layer is in-plane.

[00120] In some embodiments, the first anti-FM layer is operable to exert exchange bias on the first FM layer. In some embodiments, the apparatus comprises: a FM bias layer deposited over the first Anti-FM layer; and an exchange coupling or bias layer deposited over the FM bias layer, wherein the exchange coupling or bias layer is coupled to the first FM layer. In some embodiments, the exchange coupling or bias layer includes one of: Ru, Cu, or Ag. In some embodiments, the first FM layer is a multi-layered perpendicular stack or a layer of one or more materials. In some embodiments, the multi-layered perpendicular stack includes a stack of at least one of: Co and Pd; Co and Ni; L10 perpendicular materials; FePt; or FeN.

[00121] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus discussed above; and a wireless interface for allowing the processor to

communicate with another device.

[00122] In another example, an apparatus is provided which comprises: a first ferromagnetic (FM) layer with magneto-strictive (MS) property; an exchange coupling layer coupled to the first FM layer; a FM bias layer coupled to the exchange coupling layer; a first anti-FM layer coupled to the FM bias layer; and a piezo-electric (PZe) layer coupled to the first anti-FM layer. In some embodiments, the PZe layer is operable to exert strain on the first FM layer. In some embodiments, the PZe layer is formed of at least one of: Pb(Zro.2 Tio.8)0 ₃ ; PbTiO?; BaTiOs; BiFeCte; υί.Ί ^' Ο..·: Polyvinylidene fluoride; or PMNPT. In some embodiments, the first FM layer is formed of at least one of: Terfenol-D (Tb _x Dyi- _x Fe2); Fei- _x Ga _x ; Coo.6Feo. ₄ ; or CoFe20 ₄ .

[00123] In some embodiments, the first FM layer is a multi-layered perpendicular stack or a layer of one or more materials. In some embodiments, the multi-layered perpendicular stack includes a stack of at least one of: Co and Pd; Co and Ni; L10 perpendicular materials; FePt; or FeN.

[00124] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus discussed above; and a wireless interface for allowing the processor to

communicate with another device.

[00125] In another example, a method is provided which comprises: applying a first voltage across a layer which is operable to exert strain on a first ferromagnetic (FM) layer, wherein the first FM layer has magneto-strictive (MS) property and is coupled to a first Anti- FM layer; applying a second voltage across the first FM layer and a second Anti-FM layer, wherein the first Anti-FM layer is positioned between the first FM layer and a piezo-electric (PZe) layer; and sensing a current through the first FM layer. In some embodiments, the method comprises switching the first FM layer via the exerted strain to out-of-plane magnetization, wherein the first Anti-FM layer has in-plane magnetization. In some embodiments, the method comprises removing application of the first voltage across the layer to remove strain on the first FM layer such that the first FM layer has an in-plane

magnetization.

[00126] In another example, an apparatus is provided which comprises: a bit-line; a first source line; a second source line; a bit-cell including: a first ferromagnetic (FM) layer with magneto-strictive (MS) property; a first anti-FM layer coupled to the first FM layer; a piezo-electric (PZe) layer coupled to the first anti-FM layer, the PZe layer coupled to the second source line (SL) via a SL electrode; a tunneling barrier layer coupled to the first FM layer; a second FM layer coupled to the tunneling barrier layer; and a second anti-FM layer coupled to the second FM layer, wherein the second anti-FM layer is directly or indirectly coupled to the bit-line; and a transistor coupled to the first SL and to the PZe layer. In some embodiments, the apparatus comprises: a word-line coupled to a gate terminal of the transistor.

[00127] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus discussed above; and a wireless interface for allowing the processor to

communicate with another device.

[00128] In another example, an apparatus is provided which comprises: means for applying a first voltage across a layer which is operable to exert strain on a first

ferromagnetic (FM) layer, wherein the first FM layer has magneto-strictive (MS) property and is coupled to a first Anti-FM layer; means for applying a second voltage across the first FM layer and a second Anti-FM layer, wherein the first Anti-FM layer is positioned between the first FM layer and a piezo-electric (PZe) layer; and means for sensing a current through the first FM layer. In some embodiments, the apparatus comprises means for switching the first FM layer via the exerted strain to out-of-plane magnetization, wherein the first Anti-FM layer has in-plane magnetization. In some embodiments, the apparatus comprises: means for removing application of the first voltage across the layer to remove strain on the first FM layer such that the first FM layer has an in-plane magnetization.

[00129] In another example, a system is provided which comprises: a processor core; a memory coupled to the processor core, the memory having an apparatus according to the apparatus discussed above; and a wireless interface for allowing the processor to

communicate with another device.

[00130] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.