Title:
TEST STRUCTURE, FORMATION METHOD THEREFOR AND SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/245822
Kind Code:
A1
Abstract:
Embodiments of the present disclosure provide a test structure, a formation method therefor and a semiconductor memory. The test structure comprises multiple word lines and multiple bit lines, and a vertical transistor is formed at the intersection location of each word line and each bit line. The test structure comprises a first region and a second region, the second region being located at an outer side of the first region, a word line in the first region not being connected to a word line in the second region, and a bit line in the first region not being connected to a bit line in the second region. Multiple vertical transistors located in the first region jointly form a test array, and a vertical transistor located in the middle of the test array is a device to be tested. Thus, by means of using vertical transistors in the first region to form a small-size test array, the influence of the high resistance of word lines/bit lines on the test result is reduced, such that the test result can more accurately characterize the performance of the device to be tested.
Inventors:
JIANG YI (CN)
XIAO DEYUAN (CN)
HAN QINGHUA (CN)
TSAI MENG-FENG (CN)
XIAO DEYUAN (CN)
HAN QINGHUA (CN)
TSAI MENG-FENG (CN)
Application Number:
PCT/CN2022/109733
Publication Date:
December 28, 2023
Filing Date:
August 02, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L23/544; G11C29/12; H01L21/66
Foreign References:
| US20040082087A1 | 2004-04-29 | |||
| US20040069989A1 | 2004-04-15 | |||
| CN101304020A | 2008-11-12 | |||
| CN105336639A | 2016-02-17 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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