THIN FILM TRANSISTOR ARRAY MANUFACTURING METHOD

WIPO Patent Application WO/2014/059713

A1

A thin film transistor array manufacturing method, comprising the following steps: forming a first patterned metallic layer (208) on a substrate (202); depositing a first insulation layer (210) to cover the first patterned metallic layer (208); forming a patterned oxide semiconductor layer (212) on the first insulation layer (210) in a thin film transistor area (204); forming a second insulation layer (213) on the first insulation layer (210) and the oxide semiconductor layer (212); etching the second insulation layer (213) in the thin film transistor area (204) to expose a part of the oxide semiconductor layer (212), and simultaneously etching the second insulation layer (213) and the first insulation layer (210) in a signal line area (206) to expose the first metallic layer (208); and forming a second patterned metallic layer (216) on the second patterned insulation layer (213) in the thin film transistor area (204), such that the second patterned metallic layer (216) is electrically connected to the oxide semiconductor layer (212), while forming the second patterned metallic layer (216) on a part of the first metallic layer (208) in the signal line area (206).

CHIANG CHENG-LUNG (CN)
CHEN PO-LIN (CN)

PCT/CN2012/084358

April 24, 2014

November 09, 2012

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SHENZHEN CHINA STAR OPTOELECT (CN)

H01L21/82; G02F1/1362

CN102024757A	2011-04-20
CN102270636A	2011-12-07
US20020041347A1	2002-04-11
US20010031510A1	2001-10-18

ESSEN PATENT & TRADEMARK AGENCY (CN)
深圳翼盛智成知识产权事务所(普通合伙) (CN)

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