| Document |
Document Title |
|
JP2007243959A |
To provide a method and system for compressing an input data stream, using an LZ77-based mechanism. The disclosed method searches for a matching sequence of already processed data bytes that is identical to a current sequence of bytes. S...
|
|
JP3977601B2 |
To provide a proxy device capable of relieving a load of a network. When reply data with the new contents is transferred from a proxy 130 on the server side to a proxy 140 to the client side and when the data as request data and to be re...
|
|
JP3976393B2 |
|
|
JP2007526539A |
Elements of the inventive development system include hardware and software objects. These objects can be instanced, ordered, parameterized, and connected in a software environment to implement different functions. Once in software, the d...
|
|
JP2007235755A |
To provide an easily usable portable telephone set for confirming the principal identity of electronic mail, and for enabling only the principal to read electronic mail transmitted to the destination of the principal. This portable telep...
|
|
JP3973557B2 |
The invention concerns a method for compressing a structured document comprising nested information elements, the document being associated with at least a tree-like structure schema (1) defining a structure of the document and comprisin...
|
|
JP2007226813A |
To provide a method for efficiently compressing/decompressing a structured document. A document is associated with at least one structure schema 1 defining a structure of the document and comprising of nested structural components, which...
|
|
JP2007524917A |
A system for selectively affecting data flow to and/or from a memory device. The system includes a first mechanism for intercepting data bound for the memory device or originating from the memory device. A second mechanism compares a dat...
|
|
JP3964389B2 |
An inventive electronic circuit includes a controller for processing a processor task as well as an energy determination means for determining the energy available to the controller. A control means of the electronic circuit controls the...
|
|
JP3953206B2 |
To securely fetch a signal being supplied in synchronization with a wide range of clock from a low to high speed by synthesizing the output of a plurality of input buffers fetching an input signal in synchronization with a plurality of i...
|
|
JP3950178B2 |
PURPOSE: To provide a FIFO buffer system contrived so as to effectively control write and read operations. CONSTITUTION: The FIFO buffers 220-280 of cascade connection successively perform the write and read operations. An expansion out ...
|
|
JP2007179384A |
To provide an information processor, an information processing method, an information processing program, and a computer readable recording medium for recording the program capable of sending and receiving text data for data exchange bet...
|
|
JP3942744B2 |
To provide an image, which is almost equal with an image at the time of generation, at the time of display while effectively using a transmission band. Concerning a game system connecting plural pieces of game terminal equipment and a ga...
|
|
JP2007518178A |
An asynchronously operated FIFO pipe-line ( 10 a-d) comprises a plurality of handshake chains functionally in parallel. Successive data items are each passed by selecting a chain dependent on a value of the data item. The FIFO pipelines ...
|
|
JP2007517334A |
A number of symbols are received in a first integrated circuit (IC) device, where these symbols have been transmitted by a second IC device and are received over a serial point to point link. These symbols include a non-data sequence tha...
|
|
JP2007164707A |
To easily reuse a data conversion design definition, which is not reused conventionally in the data conversion design definition.This data conversion design unit or the like has a conversion source file definition information acquiring p...
|
|
JP2007164708A |
To provide a conversion data generator, a data conversion system, methods therefor, and programs therefor, capable of converting efficiently data of the same content as the data converted in the past.This conversion data generator 2 or t...
|
|
JP3937086B2 |
To convert a plurality of input data sequences of different data width into output data sequences of a specified data width without converting into serial data. The data sequence conversion circuit receiving an arbitrary input data seque...
|
|
JP3935952B2 |
An adaptive compression technique which is an improvement to Lempel-Ziv (LZ) compression techniques, both as applied for purposes of reducing required storage space and for reducing the transmission time associated with transferring data...
|
|
JP3934290B2 |
To reduce a decrease in operation efficiency even if block data can not be inputted at specific intervals and to perform a two-dimensional transformation processing by a small-scale circuit. A single eight-point orthogonal transformation...
|
|
JP3934157B2 |
A method and apparatus for determining the status of a resource shared by multiple subsystems operating in mutually asynchronous clock domains apply a one-bit counter for each subsystem and synchronize the value of each such bit counter ...
|
|
JP3935286B2 |
To obtain the buffer of small size which operates effectively for burst- mode writing and non-burst mode writing by providing a flag field, which is so set as to indicate which of an address or data value is stored in each line of the wr...
|
|
JP2007148622A |
To connect semiconductor integrated circuits which differ in an endian of data, an order of sequence of nibbles of data, ascending/descending orders of bits of data without making terminals of semiconductor integrated circuits increase, ...
|
|
JP3931384B2 |
To enhance effective data transfer speed by continuously transferring pieces of data with different kinds of data width regarding a FIFO memory controller. The FIFO memory controller to write and read the data to be inputted through a bu...
|
|
JP3931491B2 |
To provide a device and a method for controlling memory capable of reducing power consumption for a static display period and to provide an information processing system and a recording medium. After a DRAM controller sequencer 22 has la...
|
|
JP2007515021A |
Methods, apparatus, and articles of manufacture for performing mathematical operations using scaled integers are disclosed. In particular, an example method identifies a scaled-integer value and determines a multiplier value and a scale ...
|
|
JP3924307B2 |
To perform a shift operation on a packed data type. An apparatus for arithmetic operation is provided with: a shifter which performs a shift operation on a first packed data having a plurality of first data elements by a shift count in o...
|
|
JP3926524B2 |
To provide an FIFO type storage device which can be constituted at low costs by reducing a circuit scale. A FIFO memory 1 is provided with a single port memory 11 capable of temporarily operating either a data wiring operation or a data ...
|
|
JP3920280B2 |
To provide a data transmitting method through an I2C router providing increased security. This method for transmitting data from a transmitter port to a destination port through the I2C router comprises capturing the I2C destination port...
|
|
JP3920002B2 |
To provide a memory bank control method in which read-out of a memory is asynchronous with write-in and outrunning of address is not caused even if read-out and write-in of a memory are performed simultaneously. A counter constituting a ...
|
|
JP3917357B2 |
To speedingly process a program for executing nonlinear conversion. Eight bit data A are inputted into a nonlinear conversion table T4 and sixteen bit converted data [T2(A)&verbar T2(A)] 61 are outputted. Eight bit data B are inputted in...
|
|
JP3913004B2 |
To provide a data compression method that can losslessly compress data at high-speed by utilizing high-speed processing of expansion. A dictionary area is reserved and initialized. A 1st storage area stores '0' when succeeding data to th...
|
|
JP2007109199A |
To facilitate materialization of system-on-chip by providing a buffer circuit allowing easy connection of an existing peripheral circuit operated by various operation clocks.This buffer device 100 includes: a buffer 110 storing at least ...
|
|
JP3910932B2 |
To compress an input sequence of data portion. Every portion of an input sequence is sequentially traversed, and whether or not a first sequence portion staring at each portion matches a second sequence portion traversed before is determ...
|
|
JP3907394B2 |
To surely update data to be required for calibration with less management burden and corresponding to the change of control in a system to perform the calibration of a source file to be required for operating a control unit. Data informa...
|
|
JP3903699B2 |
To provide a method and an apparatus for data exchange which decrease the rate of the occupation of a bus in actual data transfer, minimizes the overhead, and further facilitates priority control and exchange capacity expansion by addres...
|
|
JP2007072923A |
To read out serial data as an inspection without changing the format of serial-parallel conversion data of a three-line serial data receiving circuit having no readout format.The serial data readout circuit is equipped with: a serial dat...
|
|
JP2007072857A |
To provide an arithmetic processing unit that ensures fewer operation cycles than double precision operations, unextended task switching time, and improved operation precision.The arithmetic processing unit includes general purpose regis...
|
|
JP2007067292A |
To provide a semiconductor device which is capable of reducing its wiring region in area and easily designed.The semiconductor device includes input pad cells 401 that transmit input signals input into an LSI chip to internal circuits. T...
|
|
JP3894280B2 |
To enhance the efficiency of encoding (compression) of XML data. A syntax (type) generator 2-1 is used to convert a DTD into ASN. 1 abstract syntax (type), and a separator 2-2 is used to separate text from XML data according to the DTD. ...
|
|
JP3887059B2 |
To detect whether or not the read and write of data whose data length is determined is abnormal to an FIFO(first-in first out) memory circuit. Each data whose data length is determined is separately written/ read to buffer memory 31 acco...
|
|
JP3887063B2 |
To control plural data paths so as to secure a desired relation between the instruction or data included in a certain path and that included in another path by specifying the connection between the 1st and 2nd control chains. An interloc...
|
|
JP3887263B2 |
To provide an IC card communication control application and an IC card system matching a multi-application system. The IC card communication control application 11 controls communication between the IC card 1 and a terminal or a server. ...
|
|
JP3884459B2 |
To improve quality for audio signals and stabilize synchronization between audio and video signals. Differences between write and read addresses in a memory part 102 are calculated by a signal synthesis part SUM, and data contents inform...
|
|
JP3882666B2 |
To simplify processing for transmitting data and to easily perform the addition or the deletion of transmission target data and a change of a transmission timing. In the electronic control unit wherein two microcomputers perform control ...
|
|
JP2007503080A |
A method is described for setting a disc speed in a disc drive apparatus ( 3 ) which is in data transfer communication ( 7 ) with a host system ( 2 ), wherein data transfer between carrier and drive apparatus takes place with a carrier/d...
|
|
JP2007503042A |
A dynamic memory buffer buffers between software applications executing on a processor and data generating and/or receiving devices in communication through the buffer with the applications. The buffer includes buffer manager for control...
|
|
JP3882300B2 |
To provide a serial data holding circuit which can flexibly deal with various changes and of which processing speed does not considerably fluctuate. In a serial data converter 1 composed of a buffer control circuit 2, buffer circuit 3 an...
|
|
JP3880807B2 |
To provide a digital filter the number of processing steps of which can be decreased by minimizing a buffer size, extending a filter coefficient memory and always starting a data read pointer from an extreme point of a ring buffer and to...
|
|
JP2007034643A |
To deal with various transmission sources and transmission destinations without changing hardware structure.A memory unit 1 is a unit used for transmission and reception of data, and is provided with a data buffer 4 which stores data out...
|
