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WO/2023/069183A1 |
Memory devices (100) may perform read operations and write operations with different bit error correction rates to satisfy a bit error correction rate. However, improving the bit error correction rate of the memory device (100) using a s...
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WO/2023/067770A1 |
This magnetic domain wall movement element comprises a wiring layer that includes a first ferromagnetic layer and extends in a first direction, a second ferromagnetic layer, and a spacer layer interposed between the wiring layer and the ...
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WO/2023/065272A1 |
A memory device includes a plurality of banks, each bank including memory cells, a plurality of cache modules, each cache module configured to store an address and a data of the respective bank, and a plurality of control modules, each c...
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WO/2023/070127A1 |
A memory stick configured for use with a processor in a computer is provided. The memory stick includes a printed circuit board with first and second sides, each of the first and second sides including eighteen memory chips, each of the ...
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WO/2023/064548A1 |
Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a fi...
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WO/2023/064055A1 |
Some memory dies in a stack can be connected externally to the stack and other memory dies in the stack can be connected internally to the stack. The memory dies that are connected externally can act as interface dies for other memory di...
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WO/2023/064855A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments, wherein the unencoded data file is a dataset for use with an EHR process; mappi...
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WO/2023/064829A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments wherein the unencoded data file is a dataset for use with a direct-coupled commu...
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WO/2023/064862A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments, wherein the unencoded data file is a dataset for use with a blockchain process;...
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WO/2023/063733A1 |
The present invention relates to a stateful logic-in-memory using silicon diodes, and the stateful logic-in-memory using silicon diodes according to an embodiment of the present invention comprises a plurality of silicon diodes each of w...
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WO/2023/064827A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments wherein the unencoded data file is a dataset for use with a short-range wireless...
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WO/2023/060475A1 |
A spintronic device, a storage unit, a storage array, and a read-write circuit, applied to the technical field of integration. The spintronic device comprises: bottom electrodes (101, 104); a spin-orbit coupling layer (102) provided on t...
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WO/2023/061036A1 |
A writing method and apparatus for an MRAM, and a circuit. The method comprises: when a 0 writing operation is performed on an MRAM, setting a resistance value of a reference resistor to be a first resistance value; within a write period...
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WO/2023/064828A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments wherein the unencoded data file is a dataset for use with a long-range wireless ...
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WO/2023/064310A1 |
Methods and devices for driving a laser diode are disclosed herein. An example method includes a boost regulator outputting a maximum boost voltage to drive a laser diode that is configured to output light within a wavelength range of 49...
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WO/2023/064244A1 |
Methods and systems are disclosed for performing operations for deforming an external mesh. The operations comprise receiving a video that includes a depiction of a real -world object. The operations comprise generating a three-dimension...
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WO/2023/064839A1 |
An electronic assembly for handling a storage module is provided. The electronic assembly includes an open frame structure having a front frame including a front opening configured to receive air, and two side rails coupled to opposite s...
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WO/2023/062987A1 |
As a lens barrel with a lens such that it is possible to improve a light reception amount at a light-receiving element in a configuration wherein a portion of light emitted from a light source is reflected by a half mirror and received b...
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WO/2023/064826A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments; mapping each of the plurality of file segments to a portion of a dictionary fil...
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WO/2023/063621A1 |
A processor included in an electronic device may be configured to: display an audio input selection screen related to a plurality of audio inputs in a multiple camera recording mode; receive a first user input for selecting an external e...
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WO/2023/064842A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments, wherein the unencoded data file is a dataset for use with a satellite-based com...
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WO/2023/064151A1 |
A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to ...
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WO/2023/064865A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments, wherein the unencoded data file is a dataset for use with a disaster recovery p...
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WO/2023/064729A1 |
A system and method for efficiently capturing data by sequential circuits across multiple operating conditions are described. In various implementations, an integrated circuit includes multiple signal arrival adjusters both at its I/O bo...
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WO/2023/064852A1 |
A computer-implemented method, computer program product and computing system for: processing an unencoded data file to identify a plurality of file segments, wherein the unencoded data file is a dataset for use with an ML process; mappin...
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WO/2023/064694A1 |
Methods, systems, and devices for cross point array architecture for multiple decks are described. A memory array may include multiple decks, such as six or eight decks. The memory array may also include sockets for coupling access lines...
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WO/2023/059772A1 |
Memory devices and methods for operating the same are provided. Generally, the device includes an array of multibit-memory-cells, each operable to store multiple bits in separate locations of a charge-trapping layer, and control-circuitr...
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WO/2023/059265A1 |
There is provided a method of programming a synaptic memory array of a neural processing core configured to perform neural network computations for a neural network. The method includes: writing an intended synaptic weight value for a gr...
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WO/2023/058242A1 |
This memory device is provided with a page formed from multiple memory cells arranged in columns on a substrate, and carries out: a page write operation for holding a hole group, which is formed by an impact-ionization phenomenon, inside...
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WO/2023/058161A1 |
In the present invention, a first semiconductor layer 1 is formed on a substrate; a vertically extending first impurity layer 3 and a second impurity layer 4 disposed on top of the first impurity layer are provided on a part of the first...
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WO/2023/059637A1 |
Systems, methods, and apparatus related to selecting memory cells in a memory array of a memory device. In one approach, bias circuitry generates a voltage on an access line used to select a memory cell for programming. During programmin...
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WO/2023/056640A1 |
The present application relates to the field of digital circuits, and provides a latch, a flip-flop, and a chip, which can decrease the number of transistors in the flip-flop. The latch comprises a signal input end, a signal output end, ...
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WO/2023/057795A1 |
The PMOS block (104) is connected between the virtual supply node (102) and output (101). The NMOS block (105) is connected between the virtual ground node (103) and output (101). The input of the balancing inverter chain (200, 300, 400)...
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WO/2023/059823A1 |
A plurality of device temperature values that are each indicative of a temperature at a respective device of a plurality of devices of a system is identified. A respective composite temperature threshold ratio is determined for each devi...
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WO/2023/056476A1 |
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure includes a first semiconductor material, a floating body semiconductor material having an internal side surface that sur...
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WO/2023/055806A1 |
A synergistic approach to mitigating crosstalk in a Dynamic Random-Access Memory (DRAM) implements the use of a random number generator to increment a counter in a probabilistic manner. The counter is formed by reclaiming bytes of a doub...
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WO/2023/053567A1 |
On a magnetic tape, a plurality of servo patterns are recorded along a longitudinal direction. The servo pattern is at least one linear magnetized area pair. The linear magnetized area pair comprises a first linear magnetized area that i...
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WO/2023/055958A1 |
Disclosed herein is a magnetic signature imprinting system including an imprinting device and a medical device having ferrous elements. The imprinting device includes an active area configured to receive the medical device. The active ar...
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WO/2023/050147A1 |
A RAID-based method capable of recovering data lost in a storage block in a memory, and a storage apparatus therefor. The memory comprises a plurality of storage blocks. The method comprises: generating check code data of a check factor ...
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WO/2023/053466A1 |
To improve the operating speed of a semiconductor storage device. The semiconductor storage device according to an embodiment of the present invention comprises: a first memory cell; a word line coupled to the gate of the first memory ce...
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WO/2023/056174A1 |
Embodiments of the disclosure are drawn to apparatuses and methods for bad row mode. The memory may prevent proper access operations (e.g., read operations) from being performed on a selected bad row of the memory as part of a bad row mo...
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WO/2023/054365A1 |
Provided is a hologram photosensitive composition capable of improving light-absorbing efficiency.　This hologram photosensitive composition contains a photopolymerizable compound, a photoinitiator, a sensitizing dye, and an alcohol hav...
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WO/2023/050863A1 |
A driving signal generation method and apparatus, a device and a readable storage medium. In the present application, the jump relation between different states in a state machine changes in due time, the number of the states involved in...
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WO/2023/051099A1 |
A display panel and a gate driving circuit and a driving method therefor. The gate driving circuit comprises multiple driving units; a first cascaded input end OUT(n-1) of a first-stage shift register (100) in each driving unit is connec...
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WO/2023/050086A1 |
A shift register and a driving method therefor, a gate driving circuit, and a display device. The shift register comprises: a pull-up control subcircuit, configured to provide a signal of a first signal end (CN) or a second signal end (C...
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WO/2023/055674A1 |
A computer-implemented method for identifying candidate videos for audio experiences may include (i) identifying a video with audio content that is a candidate for an audio-primary user experience that enables users to consume the video ...
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WO/2023/051903A1 |
An electronic circuit and method for self-diagnosis of a data memory (RAM) is described comprising/using a first error correction code unit (ECCGEN1) for generating an error correction code (ECCIN) from user data (DIN) to be written into...
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WO/2023/052316A1 |
A method of manufacturing a low program voltage flash memory cell with an embedded heater in the control gate creates, on a common device substrate, a conventional flash memory cell in a conventional flash memory area (CFMA), and a neuro...
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WO/2023/049221A1 |
Examples of a load beam are described herein that include a lifter tab extending towards a distal end, a dustpan defined by a dustpan forming line at a proximal end and the lifter tab at a distal end and a first and second plurality of r...
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WO/2023/048962A1 |
A memory is provided that is configured to practice two different modes of read operation, such as both a normal read operation and a burst-mode read operation. In one example, the memory is a pseudo-dual-port memory. The memory may incl...
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