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WO/1997/006624A1 |
An encoder for matched spectral null binary codes is described, particularly for 12B/15B codes. The codeword trellis is partitioned into two or more subtrellises, and each subtrellis is encoded separately. The codeword is the concatenati...
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WO/1996/036129A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036127A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036122A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder (304) for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data t...
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WO/1996/036130A1 |
An encoding system uses a modified 8/9 rate modulation code to encode 8-bit data symbols into 9-bit cells in a conventional manner in accordance with the modified code and 9-bit ECC symbols into 10-bit cells by (i) encoding 8 bits of the...
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WO/1996/036116A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder (304) for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data t...
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WO/1996/036118A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder (304) for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data t...
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WO/1996/036124A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036119A1 |
A system for enconding digital data with an M-ary (d,k) code to provide multi-level coded data where M > 2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to p...
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WO/1996/036117A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder (304) for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data t...
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WO/1996/036125A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036126A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M > 2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to pr...
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WO/1996/036121A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036115A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder (304) for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data t...
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WO/1996/036128A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036123A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/036120A1 |
A system for encoding digital data with an M-ary (d,k) code to provide multi-level coded data where M>2 comprises an M-ary (d,k) encoder for accepting digital input data. The M-ary (d,k) coder (304) encodes the digital input data to prod...
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WO/1996/032780A1 |
Source data of m bits are converted into conversion codes of n (n>m) bits and the inversion is also possible. The kinds of 15-bit codes which are the conversion codes of tables A-F and the caracteristic parts of the contents of the codes...
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WO/1996/032779A1 |
The information to be recorded is divided into 8-bit long data words. Each data word is then converted to 14-bit long code word. The code words are sequentially connected with a one-bit merging bit inserted between the code words to defi...
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WO/1996/031881A1 |
A data transmission apparatus for transmitting an original data has a converter for converting the original data to sequential data codes. The data code is formed by a combination of HIGH level binary codes and LOW level binary codes. Th...
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WO/1996/031963A1 |
An ATV system (16, 18, 20) encodes variable length elementary streams of data into a multilevel symbol signal comprising a plurality of multiplexed fixed length data packets without sync information. The fixed length data packets are arr...
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WO/1996/024987A1 |
An encoding arrangement for encoding (n-1)-bit information words into n-bit channel words so as to obtain a channel signal of concatenated channel words is disclosed. The channel signal is a bit sequence having the virtue that at most k ...
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WO/1996/024194A1 |
An encoding arrangement for encoding a sequence of (n-1)-bit information words into a sequence of n-bit channel words is disclosed, comprising input means (1) for receiving the information words, converter means (2) for converting the (n...
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WO/1996/021277A1 |
A NULL convention threshold gate (921) receives a plurality of inputs (X1, X2, ...Xn), each having an asserted state and a NULL state. The threshold gate switches its output (Z) to an asserted state when the number of asserted inputs exc...
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WO/1996/019044A1 |
A data encoding method by which a data word train constituted in units of (m x i) bits is converted into a code word train in units of (n x i) bits. In the method, a shift register (1) receives a data word train in units of (m x i) bits ...
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WO/1996/012364A1 |
A modulation scheme and system, compatible with both the asynchronous IRDA mode and the synchronous mode of IR communication, involves Non-Return-to-Zero-Inverted (NRZI) and Flash pulse encoding in conjunction with zero-bit stuffing. A d...
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WO/1996/010255A1 |
An encoder includes a control bit insertion circuit (12) for adding a control bit to input data, which is then subjected to I-NRZ modulation by a precoder (14) to generate a reference code. The reference code is given to a 4-code generat...
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WO/1996/004739A1 |
Method for decoding a multivalent electrical signal which can take a number n of states greater than two. An electrical magnitude, representative of the signal state in successive plateau periods (T1, T2, T3... Ti) of constant time T dur...
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WO/1996/002054A1 |
The present invention uses a conversion table a part of which is duplexed in order to directly convert input M-bit data into an N-bit code without using a margin bit. This conversion table comprises first and second sub-tables each inclu...
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WO/1995/032553A1 |
An apparatus and method for transmitting an 8-bit binary format data word as a 6-trit ternary code word includes an encoder (13), a decoder (178), and a code assignment that produce, for each 8-bit data word value, a unique 6-trit ternar...
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WO/1995/028050A1 |
A system for determining the data bits represented by the received symbols of one or more data constellations includes converting the received symbols into multi-bit values (preferably in two's complement form), selecting a number of the...
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WO/1995/027284A1 |
The application relates to a method of converting a sequence of m-bit information words (1) to a modulated binary signal (7). For each received information word (1) from the sequence is delivered an n-bit code word (4). The delivered cod...
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WO/1995/022802A2 |
The Patent Applications relates to a method of converting a series of m-bit information words (1) to a modulated signal (7). For each information word from the series an n-bit code word (4) is delivered. The delivered code words (4) are ...
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WO/1995/018494A1 |
A data frame structure for variable size data constellations includes repetitive data segments each containing a fixed number of symbols arranged as a data segment sync character and data bytes. The frame includes a header segment includ...
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WO/1995/010885A1 |
A method and apparatus for demodulating a pulse width modulated (PWM) signal previously modulated with either a first or second data value comprises sensing an actual duration of the first period of the bit cell, and generating an actual...
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WO/1995/009486A1 |
A method for mapping the serial 0 and 1 pulses received at a known clock rate from a Delta Sigma Modulator. All 0's are generated at the output when no 11 pairs are present in the input signal during the sampled clock periods. A 1 is gen...
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WO/1995/002291A1 |
An improved precoding technique (700) and device (100) allows transmission of a signal point sequence over a channel h(D) to provide efficient data transfer in the presence of intersymbol interference and noise at data rates approaching ...
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WO/1995/002283A1 |
A method of coding, and a coder, using a code in which data words are assigned to code word pairs in a selective manner, so that the value of a data word error resulting from inversion of a bit in a code word may be specific to and depen...
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WO/1994/026048A1 |
The invention relates to a method for including auxiliary data in a data signal encoded with a bipolar in-line code, comprising recognizing an unambiguously recognizable, predetermined bit pattern from a data signal, and generating an un...
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WO/1994/016390A1 |
The present invention provides a method and apparatus for transmitting NRZ data signals across an interface comprising an isolation barrier disposed between two devices interconnected via a bus. The apparatus comprises a signal different...
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WO/1994/011952A1 |
In a digital audio or digital video recording channel, a pseudo clock extractor receives a reference clock (212, 306) having a periodicity n times (n 4) or preferably 2n times (n 2) the frequency of an audio data clock signal, the refere...
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WO/1994/011989A1 |
Methods and apparatus for encoding and decoding information in broadcast or recorded segment signals are described. In certain embodiment, an audience monitoring system encodes identification information x(w) in the audio signal portion ...
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WO/1994/001953A1 |
A method and apparatus is described for decoding a data stream in Manchester I encoded format with an ANSI sync, wherein the apparatus includes a first counter for counting clock pulses for a one-half data bit cell interval in increments...
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WO/1993/022841A1 |
A circuit for decoding a bi-phase mark signal comprises a circuit (2, 3) for detecting transitions in the signal, a counter (4) for producing an output signal proportional to the period between consecutive transitions in the signal, and ...
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WO/1993/017417A1 |
A recording medium on which information data is optically recorded. In the recording region of the optical recording medium, the space between the n-th recording track and the preceding (n-1)-th recording track is smaller than the diamet...
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WO/1993/015558A2 |
This invention relates to devices to compact data, and to transmit, store, compute with and cross-reference this compacted data. It is particularly concerned with a system of computing devices which accepts any quantity of information fr...
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WO/1993/012599A1 |
In this embedded signalling system a sequence of code symbols representing digital information is generated (100). A code signal representing this sequence is generated (200), which is dynamically filtered to form a modified code signal ...
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WO/1993/009493A1 |
A method to encode two digital signals (USC-B, UBC-B) is disclosed. Each of the digital signals is characterized by a bit stream. An N bit block from the first signal is mapped to a unique M bit third signal where M is greater than N. Fu...
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WO/1993/009604A1 |
A run length limited encoding/decoding system (200) of this invention includes a clock swap logic circuit (301), a read reference clock multiplexer circuit (304), a write clock skip logic circuit (310), an encoder start logic circuit (34...
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WO/1993/001591A1 |
A method and apparatus for error detection and correction in the storage and retrieval of digital data on magnetic storage systems includes forming and storing a set of reference waveforms (... Wn-1, Wn, Wn+1, ...) having assigned refere...
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