Title:
集積回路デバイスに歪みを与える技術及び構成
Document Type and Number:
Japanese Patent JP2013513945
Kind Code:
A
Abstract:
Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a first barrier layer coupled with the semiconductor substrate, a quantum well channel coupled to the first barrier layer, the quantum well channel comprising a first material having a first lattice constant, and a source structure coupled to the quantum well channel, the source structure comprising a second material having a second lattice constant, wherein the second lattice constant is different than the first lattice constant to impart a strain on the quantum well channel. Other embodiments may be described and/or claimed.
Inventors:
Radsavrievic, Marco
Dewey, Gilbert
Mukherjee, Niroy
Pilarisetti, Ravi
Dewey, Gilbert
Mukherjee, Niroy
Pilarisetti, Ravi
Application Number:
JP2012543165A
Publication Date:
April 22, 2013
Filing Date:
December 02, 2010
Export Citation:
Assignee:
Intel Corporation
International Classes:
H01L21/338; H01L21/336; H01L27/095; H01L29/778; H01L29/78; H01L29/812
Domestic Patent References:
| JP2011114336A | 2011-06-09 | |||
| JP2005217391A | 2005-08-11 | |||
| JP2005286341A | 2005-10-13 | |||
| JPH09270522A | 1997-10-14 | |||
| JP2009105163A | 2009-05-14 | |||
| JP2009212413A | 2009-09-17 | |||
| JP2009283527A | 2009-12-03 |
Foreign References:
| US0008014A | 1851-04-01 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki