Title:
裏面モールド構成(BSMC)の使用によるパッケージの反りおよび接続の信頼性を向上させるためのプロセス
Document Type and Number:
Japanese Patent JP2013530523
Kind Code:
A
Abstract:
A backside mold configuration (BSMC) process for manufacturing packaged integrated circuits includes applying a mold compound to a side of a packaging substrate opposite an attached die. The mold compound is deposited on a dielectric (such as photo resist). The mold compound and dielectric are patterned after coupling a die to the packaging substrate to expose a contact pad of the packaging substrate. After patterning the mold compound and dielectric, a packaging connection is coupled to contact pads through the mold compound and dielectric. The mold compound surrounding the packaging connection reduces warpage of the packaging substrate during processing. Additionally, patterning the dielectric after attaching the die improves reliability of the packaging connection.
Inventors:
Omar Jay Bushir
Milind Pee Char
Sasidar Mova
Milind Pee Char
Sasidar Mova
Application Number:
JP2013510368A
Publication Date:
July 25, 2013
Filing Date:
May 19, 2011
Export Citation:
Assignee:
Qualcomm, Inc.
International Classes:
H01L23/12; H01L21/56; H05K1/18
Domestic Patent References:
| JP2004240233A | 2004-08-26 | |||
| JP2009094195A | 2009-04-30 | |||
| JP2000150557A | 2000-05-30 | |||
| JP2007281301A | 2007-10-25 | |||
| JP2002343931A | 2002-11-29 |
Attorney, Agent or Firm:
Yasuhiko Murayama
Kuroda Shinpei
Kuroda Shinpei