Title:
【発明の名称】ア―ビトレ―ション・システム
Document Type and Number:
Japanese Patent JP2539964
Kind Code:
B2
Abstract:
Bus master for use in computer system includes logic for determining the number of words remaining to be transferred in a DMA operation to supply signals to permit arbitration to start for the next DMA request, thereby avoiding an idle cycle . A timeout state machine is also included to prevent the bus master state machine from hanging in a state with no exit. Errors can be masked to permit analysis of system problems.
More Like This:
| JPH0756803 | HIGH-SPEED DMA TRANSFER DEVICE |
| JPS59188879 | DATA PROCESSOR |
| JP3781634 | IMAGE PROCESSOR, IMAGE PROCESSING METHOD AND PORTABLE VIDEO EQUIPMENT |
Inventors:
RISA RIN FUITSUSHAA
SUTEIIBUN DEERU HANNA
SUTEIIBUN DEERU HANNA
Application Number:
JP17878591A
Publication Date:
October 02, 1996
Filing Date:
June 24, 1991
Export Citation:
Assignee:
INTAANASHONARU BIJINESU MASHIINZU CORP
International Classes:
G06F13/28; G06F13/30; G06F13/362; G06F13/368; (IPC1-7): G06F13/28
Attorney, Agent or Firm:
Koichi Tonmiya (1 person outside)