Title:
【発明の名称】Dフリップフロップ回路
Document Type and Number:
Japanese Patent JP2623889
Kind Code:
B2
Abstract:
PURPOSE:To speech up an operation with simple circuit constitution by adopting the constitution of a master flip-flop part and a slave flip-flop part provided respectively with a multi-input combination logic circuit elements and adding a logic arithmetic function to the D flip-flop. CONSTITUTION:The flip-flop circuit is provided with plural master flip-flop sections 1A, 1B and a slave flip-flop section 2 receiving the output signal of the master flip-flop sections. Then each of the master flip-flop sections 1A, 1B and the slave flip-flop section 2 are provided respectively with a logic circuit element applying nonlogic operation to plural input signals. Moreover, the sections are provided with inverters I1-I3, and selective circuits 11A, 11B selecting a signal inputted to the logic circuit as for whether the signal is inputted to the output of the inverter or the outputs of the input signal or the master flip- flop sections 1A, 1B according to the clock signal. Since the logic calculation function is provided in such a manner, the delay time of the logic circuit is shortened to speed up the circuit operation.
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Inventors:
Fuyuki Okamoto
Application Number:
JP3519690A
Publication Date:
June 25, 1997
Filing Date:
February 16, 1990
Export Citation:
Assignee:
NEC
International Classes:
H03K3/3562; H03K3/037; H03K3/356; (IPC1-7): H03K3/037; H03K3/3562
Domestic Patent References:
| JP5871717A | ||||
| JP63282531A | ||||
| JP61263313A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)