Title:
【発明の名称】シリアルインターフェイス回路
Document Type and Number:
Japanese Patent JP3047500
Kind Code:
B2
Abstract:
PURPOSE:To easily set a pattern of a channel status into a specific pattern used frequently for a job use not through a CPU, to reduce the setting man-hour and time and to decrease power consumption. CONSTITUTION:A channel status register 12 latches and outputs a channel status data representing a sampling frequency or its application and its output is set to a prescribed value by using a preset signal. The channel status register 12 outputs the channel status data obtained in this way by using a clock from a block counter 15. A shift register 14 stores a digital audio signal and the channel status data with an error correction code added thereto by a CRCC circuit 13 once and outputs them as a serial data in an AES/EBU format.
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Inventors:
Shinji Matsunaka
Mamoru Ueda
Mamoru Ueda
Application Number:
JP10649291A
Publication Date:
May 29, 2000
Filing Date:
April 12, 1991
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H04N5/60; H04N5/91; H04N5/92; H04N19/00; H04N19/423; H04N19/46; H04N19/65; H04N19/70; (IPC1-7): H04N5/91; H04N5/92; H04N7/24
Attorney, Agent or Firm:
Akira Koike (3 others)