Title:
【発明の名称】フラッシュ・イーピーロム集積回路構造
Document Type and Number:
Japanese Patent JP3260761
Kind Code:
B2
Abstract:
Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes a memory array having at least M rows and 2N columns of flash EPROM cells. M word lines, each coupled to the flash EPROM cells in one of the M rows of the flash EPROM cells, and N global bit lines are included. Data in and out circuitry is coupled to the N global bit lines which provide for reading and writing data in the memory array. Selector circuitry, coupled to the 2N columns of flash EPROM cells, and to the N global bit lines, provides for selective connection of two columns of the 2N columns to each of the N global bit lines so that access to the 2N columns of flash EPROM cells by the data in and out circuitry is provided across N global bit lines. The semiconductor substrate has a first conductivity type, a first well in the substrate of a second conductivity type, and a second well of the first conductivity type in the first well. The flash EPROM cells are made in the second well to allow application of a negative potential to at least one of the source and drain during an operation to charge the floating gate in the cells.
Inventors:
Yu, Tom Dunn-Singh
Futia
Lynn, Thien-Rah
One, Ray Elle
Futia
Lynn, Thien-Rah
One, Ray Elle
Application Number:
JP51013396A
Publication Date:
February 25, 2002
Filing Date:
September 13, 1994
Export Citation:
Assignee:
Macronix International Company Limited
International Classes:
G11C17/00; G08G1/017; G11C8/12; G11C16/02; G11C16/04; G11C16/10; G11C16/16; G11C17/12; H01L21/8247; H01L27/115; H01L29/788; H01L29/792; (IPC1-7): G11C16/04; G11C17/12
Domestic Patent References:
| JP555530A |
Attorney, Agent or Firm:
Hanawa Yoshio