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Title:
【発明の名称】半導体装置
Document Type and Number:
Japanese Patent JP3340690
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To stabilize the operation of a voltage limiter circuit by including a MOS capacitor whose threshold voltage is negative in an internal voltage generating circuit generating internal voltages by receiving an operating power source voltage. SOLUTION: In drive circuits 7a, 7b, when wirings of outputs of the circuits intersect a wiring 12a, a feedback circuit is generated via the parasitic capacitance CC3 between wirings and operations of the circuits becomes unstable. In order to prevent this unstableness, the gain of a loop is made to be sufficiently small by inserting capacitors CR1 , CR2 whose capacitances are sufficiently larger than parastic capacitances CC1 to CC3 . Capacitors to be used in here are formed between gates and a substrate surface across a gate insulating film and large capacitances can be obtained with relatively small areas by using a thin gate insulating film as a capacitor insulating film. Since there are wells under the gates, the threshold voltage of the capacitors is negative and capacitances of the capacitors becomes roughly constant as long as a voltage of one direction is applied on them so that sides of gates become positive.

Inventors:
Masashi Horiguchi
Masakazu Aoki
Kiyoo Ito
Yoshinobu Nakagome
Shinichi Ikenaga
Eto Jun
Norio Miyake
Takaaki Noda
Hitoshi Tanaka
Application Number:
JP2964899A
Publication Date:
November 05, 2002
Filing Date:
February 08, 1999
Export Citation:
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Assignee:
株式会社日立製作所
株式会社日立超エル・エス・アイ・システムズ
International Classes:
G11C11/413; G11C11/407; H01L21/8242; H01L27/108; (IPC1-7): G11C11/407; G11C11/413; H01L21/8242; H01L27/108
Domestic Patent References:
JP62121990A
JP61262078A
JP56148859A
Attorney, Agent or Firm:
Yasuo Sakuta