Title:
【発明の名称】集積回路製造に際し高純度銅から成る導体構造を電解形成するための方法
Document Type and Number:
Japanese Patent JP3374130
Kind Code:
B2
Abstract:
A method is disclosed for electrolytically forming conductor structures from highly pure copper on surfaces of semiconductor substrates, which surfaces are provided with recesses, when producing integrated circuits. The method includes the steps of coating the surfaces of the semiconductor substrates with a full-surface basic metal layer in order to achieve sufficient conductance for the electrolytic depositions, depositing full-surface deposition of copper layers of uniform layer thickness on the basic metal layer by an electrolytic metal deposition method, and structuring the copper layer. The electrolytic metal deposition method is accomplished by bringing the semiconductor substrates into contact with a copper deposition bath containing at least one copper ion source, at least one additive compound for controlling the physico-mechanical properties of the copper layers, and Fe(II) and/or Fe(III) compounds, and applying an electric voltage between the semiconductor substrates and dimensionally stable counter-electrodes.
More Like This:
Inventors:
Meyer Heinrich
Teeth Andreas
Teeth Andreas
Application Number:
JP2000595378A
Publication Date:
February 04, 2003
Filing Date:
January 11, 2000
Export Citation:
Assignee:
Atotehi Deutschland Gesellschaft Mitt Beschlenktel Haftung
International Classes:
C25D5/18; C25D3/38; C25D7/12; H01L21/28; H01L21/288; H01L21/3205; H01L21/768; H01L23/52; (IPC1-7): C25D7/12
Domestic Patent References:
| JP10321561A | ||||
| JP246675B2 | ||||
| JP8507106A | ||||
| JP2000500529A |
Other References:
【文献】国際公開97/19206(WO,A1)
Attorney, Agent or Firm:
Takehisa Ito (1 outside)