Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
チェック回路を含む集積回路
Document Type and Number:
Japanese Patent JP3377225
Kind Code:
B2
Abstract:
An integrated circuit (IC) chip which can be tested even after being packaged on a circuit board together with other IC chips, and a method of testing such IC chips on the circuit board are provided. The IC chip has a main IC section to which a particular function is assigned, and a plurality of testing circuits capable of freely extracting output data of the main IC section on a common bus. An interface is also provided on the IC chip which receives signals for controlling the testing circuits from the outside. The testing circuits, therefore, can selectively hold data sent from the outside or data from the main IC section and then send the data out via input/output terminals thereof or the interface.

Inventors:
Adachi A scent
Application Number:
JP8564992A
Publication Date:
February 17, 2003
Filing Date:
April 07, 1992
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
富士写真フイルム株式会社
International Classes:
G06F11/273; H01L21/66; G01R31/28; (IPC1-7): G01R31/28
Attorney, Agent or Firm:
Takao Katori



 
Previous Patent: 真空ポンプの排気方法

Next Patent: エコー装置