Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP3574041
Kind Code:
B2
Abstract:
The present invention implements a decrease in chip size. The device is comprised of memory cell arrays 34a and 34b, a bank selector 36, a cell select circuit 38a, a data multiplexer 40, and an input/output buffer 42. The bank selector generates a bank select signal and selects the memory cell arrays alternately. The cell select circuit selects a predetermined memory cell of the memory cell array selected by the bank select signal and performs a read operation from and a write operation to this memory cell. The data multiplexer transfers the read data from the memory cell array selected by the bank select signal to the input/output buffer.
Inventors:
Akira Nakayama
Yuichi Matsushita
Yuichi Matsushita
Application Number:
JP2000127083A
Publication Date:
October 06, 2004
Filing Date:
April 27, 2000
Export Citation:
Assignee:
Oki Micro Design Co., Ltd.
Oki Electric Industry Co., Ltd.
Oki Electric Industry Co., Ltd.
International Classes:
G11C7/00; G11C8/12; G11C11/401; G11C11/407; G11C11/413; G11C11/41; (IPC1-7): G11C11/41; G11C7/00; G11C11/401; G11C11/407; G11C11/413
Domestic Patent References:
| JP61142814A | ||||
| JP5135583A | ||||
| JP9231755A | ||||
| JP5089678A | ||||
| JP7161183A |
Attorney, Agent or Firm:
Takashi Ogaki