Title:
パイプライン方式のプロセッサにおける例外処理
Document Type and Number:
Japanese Patent JP3781419
Kind Code:
B2
Abstract:
A programmable processor includes a execution pipeline and an exception pipeline. The execution pipeline may be a multi-stage execution pipeline that processes instructions. The exception pipeline may be a multi-stage exception pipeline that propagates exceptions resulting from the execution of the instructions. The execution and exception pipelines may have the same number of stages and may operate on the same clock cycles. When an instruction passes from a stage of the execution pipeline to a later stage of the execution pipeline, an exception may similarly pass from a corresponding stage of the exception pipeline to a corresponding later stage of the exception pipeline.
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Inventors:
Ross, charles, pee
Shin, Ravi, Pee
Overcomp, Gregory, A
Shin, Ravi, Pee
Overcomp, Gregory, A
Application Number:
JP2002550517A
Publication Date:
May 31, 2006
Filing Date:
December 10, 2001
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F9/38; G06F9/48
Domestic Patent References:
| JP236422A | ||||
| JP6421629A |
Attorney, Agent or Firm:
Masanori Honjo
Yoshiko Honjo
Yoshiko Honjo
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