Title:
強誘電体メモリ
Document Type and Number:
Japanese Patent JP4157553
Kind Code:
B2
Abstract:
For a predetermined period from the start of a read operation, an electric current is fed to bit lines connected with memory cells so that ferroelectric capacitors of the memory cells are charged. The voltage change of the bit lines are different according to the logic values of data stored in the ferroelectric capacitors. Therefore, the logic value stored in the memory cells can be detected as a time difference. Even if the voltage change of the bit lines is small, the time difference can be reliably generated. Even in case the residual dielectric polarization value of the ferroelectric capacitor is low, therefore, the data can be reliably read from the memory cells. In short, the read margin of data can be better improved than in the case where the logic value of data is detected with a voltage difference.
Inventors:
Shandra travis
Sheikh Horace Lami Ali
Shoichi Masui
Sheikh Horace Lami Ali
Shoichi Masui
Application Number:
JP2005500197A
Publication Date:
October 01, 2008
Filing Date:
May 27, 2003
Export Citation:
Assignee:
富士通株式会社
International Classes:
G11C11/22; G11C29/02
Domestic Patent References:
| JP2002032984A | ||||
| JP11185465A | ||||
| JP10214488A | ||||
| JP2001344962A | ||||
| JP2000187990A |
Attorney, Agent or Firm:
Furuya Fumio