To solve the problem wherein the deviations in the consumption-current distribution, when a consumption current is increased partially on a semiconductor integrated circuit, has not been taken into consideration by layout designing methods.

In the layout designing method for a semiconductor integrated circuit, a power connecting cell electrically connecting an uppermost-layer wiring and a lower-layer wiring is arranged. The layout designing method has a process, in which the arrangement of a plurality of functional blocks on the semiconductor integrated circuit is set, and the process in which a plurality of the power-connecting cells are disposed in a semiconductor integrated-circuit forming region on the outsides of functional-block arranging regions. The layout designing method further has a process, in which the effect of the voltage drop of the uppermost-layer wiring is analyzed on the basis of the disposal of the power connecting cells.

COPYRIGHT: (C)2006,JPO&NCIPI