Title:
ＳＦＥＮＣＥを用いずに最適化されたＰＩＯ書込みシーケンスを用いるパケット送信
Document Type and Number:
Japanese Patent JP6377844
Kind Code:
B2
Abstract:
Method and apparatus for sending packets using optimized PIO write sequences without sfences. Sequences of Programmed Input/Output (PIO) write instructions to write packet data to a PIO send memory are received at a processor supporting out of order execution. The PIO write instructions are received in an original order and executed out of order, with each PIO write instruction writing a store unit of data to a store buffer or a store block of data to the store buffer. Logic is provided for the store buffer to detect when store blocks are filled, resulting in the data in those store blocks being drained via PCIe posted writes that are written to send blocks in the PIO send memory at addresses defined by the PIO write instructions. Logic is employed for detecting the fill size of packets and when a packet's send blocks have been filled, enabling the packet data to be eligible for egress.
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Inventors:
De badge, mark
Muta, Yatin M.
Muta, Yatin M.
Application Number:
JP2017516268A
Publication Date:
August 22, 2018
Filing Date:
June 05, 2015
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F13/38; G06F13/12
Domestic Patent References:
| JP2007287142A |
Foreign References:
| US20110145450 | ||||
| US8122177 |
Attorney, Agent or Firm:
Tadashige Ito
Tadahiko Ito
Shinsuke Onuki
Tadahiko Ito
Shinsuke Onuki