Title:
ストレージシステム及び記憶制御方法
Document Type and Number:
Japanese Patent JP6681512
Kind Code:
B2
Abstract:
This storage system has one or more non-volatile memory devices and a processor unit that comprises one or more processors connected to the one or more non-volatile memory devices. At least a portion of the non-volatile memory of each of the one or more non-volatile memory devices comprises a user area, which is a storage area to which data is written, and an update area, which is a storage area to which update data for the original data is written. The processor unit changes the user capacity, namely the capacity of the user area, of each of the one or more non-volatile memory devices on the basis of at least one of one or more resource usage rates of the one or more non-volatile memory devices.
Inventors:
Naoya Machida
Honma Shigeo
Honma Shigeo
Application Number:
JP2019500143A
Publication Date:
April 15, 2020
Filing Date:
February 20, 2017
Export Citation:
Assignee:
株式会社日立製作所
International Classes:
G06F12/02; G06F3/06; G06F3/08; G06F12/00
Domestic Patent References:
| JP2016507816A | ||||
| JP2016162397A | ||||
| JP2014513356A |
Foreign References:
| US20110099320 | ||||
| WO2016181528A1 |
Attorney, Agent or Firm:
Wilfort International Patent Office