Title:
半導体装置の作製方法
Document Type and Number:
Japanese Patent JP6796411
Kind Code:
B2
Abstract:
A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
Inventors:
Yuta Endo
Hideomi Suzawa
Yuro Tezuka
Tetsuhiro Tanaka
Toshiya Endo
Mitsuhiro Ichijo
Hideomi Suzawa
Yuro Tezuka
Tetsuhiro Tanaka
Toshiya Endo
Mitsuhiro Ichijo
Application Number:
JP2016129091A
Publication Date:
December 09, 2020
Filing Date:
June 29, 2016
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; H01L29/786
Domestic Patent References:
| JP2012049514A | ||||
| JP2014209593A | ||||
| JP2015109425A | ||||
| JP2013251534A | ||||
| JP2013149963A | ||||
| JP2008546173A | ||||
| JP2013062529A |